SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
RFTCLK Select Register
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| Instance Name | Physical Address |
|---|---|
| CPSW0 | 0803 D008h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RFTCLK_SEL | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:5 | RESERVED | NONE | 0h | Reserved |
| 4:0 | RFTCLK_SEL | R/W | 0h | Reference clock select.
This bit field is used to control an external multiplexer that selects one out of 8 clocks for time sync reference. 0h Selects CPSWHSDIV_CLKOUT2 clock
1h Selects MAINHSDIV_CLKOUT3 clock
2h Selects MCU_CPTS0_RFT_CLK I/O pin
3h Selects CPTS0_RFT_CLK I/O pin
4h Selects MCU_EXT_REFCLK0 I/O pin
5h Selects EXT_REFCLK1 I/O pin
6h Selects PCIE0_TXI0_CLK clock
7h Selects PCIE1_TXI0_CLK clock The RFTCLK_SEL
value can be written only when the [0]
CPTS_EN and [3] TSTAMP_EN bits are cleared
to zero in the CPSW_CPTS_CONTROL_REG
register. |