SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Time Stamp Load Enable Register
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| Instance Name | Physical Address |
|---|---|
| CPSW0 | 0803 D014h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TS_LOAD_EN | ||||||
| NONE | W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:1 | RESERVED | NONE | 0h | Reserved |
| 0 | TS_LOAD_EN | W | 0h | Time Stamp Load Enable. Writing a one to this bit enables the time stamp value to be written with the value in CPSW_CPTS_TS_LOAD_VAL_REG/ CPSW_CPTS_TS_LOAD_HIGH_VAL_REG. This bit is write only and will be cleared by the hardware after one clock. The upper 32-bits of the time stamp (CPSW_CPTS_TS_LOAD_HIGH_VAL_REG) are forced to zero in 32-bit mode. |