SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Time Stamp Comparison High Value Register
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| Instance Name | Physical Address |
|---|---|
| CPSW0 | 0803 D048h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| TS_COMP_HIGH_VAL | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TS_COMP_HIGH_VAL | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| TS_COMP_HIGH_VAL | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TS_COMP_HIGH_VAL | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | TS_COMP_HIGH_VAL | R/W | 0h | Time Stamp Comparison High Value. Writing a non-zero value to the CPSW_CPTS_TS_COMP_LEN_REG[31-0] TS_COMP_LENGTH register causes a pulse of TS_COMP_LENGTH RCLK periods on the TS_COMP output and a comparison event when the [31-0]TIME_STAMP counter value is equivalent to CPSW_CPTS_TS_COMP_VAL_REG[31-0] TS_COMP_VAL and CPSW_CPTS_TS_COMP_HIGH_VAL_REG[31-0] TS_COMP_HIGH_VAL. This value is unused in 32-bit mode. The upper 32-bits in CPSW_CPTS_TS_COMP_HIGH_VAL_REG register should be written before the lower 32-bits in the CPSW_CPTS_TS_COMP_VAL_REG register. |