SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register determines how the ordinal local event is translated to a global event on the outgoing event transport lane. Both pulse and rising edge local event types are supported. With pulsed events, the event count is determined by the number of cycles for which the event signal remains high. For rising edge events, the count represents the total number of rising edge transitions. The index field of the register determines the outgoing global event index, and the mode bit specifies either pulsed or rising edge local event detection.
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| Instance Name | Physical Address |
|---|---|
| DMASS0_INTAGGR_0 | 4812 0000h + formula |
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 48 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| GEVIDX | |||||||
| R/W | |||||||
| FFFFh | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GEVIDX | |||||||
| R/W | |||||||
| FFFFh | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 63:32 | RESERVED | NONE | 0h | Reserved |
| 31 | MODE | R/W | 0h | Local event detection mode. This field is set to 0 for pulsed events, and to 1 for rising edge eventss Reset Source: srst_n |
| 30:16 | RESERVED | NONE | 0h | Reserved |
| 15:0 | GEVIDX | R/W | FFFFh | Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable. Reset Source: srst_n |