SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is used to initialize FOTA logic including M8051EW MCU
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| Instance Name | Physical Address |
|---|---|
| FSS0 | 0FC6 0000h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | MCU_STALL_EN | FUNC_MODE | PDMEM_INIT_DONE | MEMACCESS | CLKDIS | RESET | |
| NONE | R/W | R/W | R | R/W | R/W | R/W | |
| 0h | 0h | 1h | 0h | 1h | 0h | 1h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:6 | RESERVED | NONE | 0h | Reserved |
| 5 | MCU_STALL_EN | R/W | 0h | Reserved field. This field SHALL be retained at 0, which is the default value. Reset Source: vbus_mod_g_rst_n |
| 4 | FUNC_MODE | R/W | 1h | This bit is used for selection functional or debug mode. 1'b1 - M8051EW uses functional mode for regular operation. 1'b0 - M8051EW uses debug mode for debug using JTAG. Reset Source: vbus_mod_g_rst_n |
| 3 | PDMEM_INIT_DONE | R | 0h | This bit indicates that FOTA program/data memory RAM initialization is done. Until this bit is set, access to program/data memory should not be performed by software. Reset Source: vbus_mod_g_rst_n |
| 2 | MEMACCESS | R/W | 1h | This bit provides SOC CPU access to program/data memory and internal memory through FSS config interface when set. If clear, these M8051EW memories are not accessible through config interface and is fully under the control of M8051EW. Software has to ensure that M8051EW is in reset by setting bit 0 of this register when memaccess is set. Reset Source: vbus_mod_g_rst_n |
| 1 | CLKDIS | R/W | 0h | This bit holds M8051EW core clock gated when set to 1'b1. Clock to M8051EW is enabled at reset. SOC software sets this bit to put M8051EW and other FOTA logic in low power state when not used by enabling clock gating. Reset Source: vbus_mod_g_rst_n |
| 0 | RESET | R/W | 1h | This bit holds M8051EW core in reset when set to 1'b1. System firmware clears this bit after setting up program and data memories. Reset Source: vbus_mod_g_rst_n |