SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The End of Interrupt (EOI) Register allows the CPU to acknowledge completion of fsas_fota_stat_intr_req pulse interrupt. When this register is written to 1'b0, INTD logic used for converting fsas_ecc_intr_err_pend level interrupt to pulse will be re-armed. That is, if interrupt sources remain after writing this register to 1'b0, another pulse interrupt will be triggered by INTD. Conversely, if this register is not written to 1'b0 after fsas_fota_stat_intr_req pulse interrupt is received, then another pulse interrupt will not be received as INTD has not been re-armed. This register will be reset one cycle after it has been written to. Please note that the reason for writing 1'b0 is because there is only one interrupt (no interrupt aggregation) associated with this EOI and the INTD vector associated with this interrupt is 1'b0.
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| Instance Name | Physical Address |
|---|---|
| FSS0 | 0FC6 0020h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | EOI_VECTOR | ||||||
| NONE | W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:1 | RESERVED | NONE | 0h | Reserved |
| 0 | EOI_VECTOR | W | 0h | Write 1'b0 to acknowledge fsas_fota_stat_intr_req pulse interrupt. Reset Source: vbus_mod_g_rst_n |