SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The IRQ_ENABLE_CLR register allows the interrupt sources to be manually disabled when writing a 1 to a specific bit. This register corresponds to fsas_fota_stat_intr_pend/fsas_fota_stat_intr_req interrupt output. Write 0: No action Write 1: Disable event Read 0: Event is disabled Read 1: Event is enabled
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| Instance Name | Physical Address |
|---|---|
| FSS0 | 0FC6 0030h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | FOTA_DONE | ||||||
| NONE | R/W1TC | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:1 | RESERVED | NONE | 0h | Reserved |
| 0 | FOTA_DONE | R/W1TC | 0h | FOTA done enable clear Reset Source: vbus_mod_g_rst_n |