SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
RAM Configuration Register
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| Instance Name | Physical Address |
|---|---|
| PBIST0 | 0039 0160h |
| PBIST1 | 003A 0160h |
| PBIST2 | 003B 0160h |
| PBIST3 | 003C 0160h |
| PBIST4 | 003D 0160h |
| PBIST5 | 003E 0160h |
| PBIST6 | 003F 0160h |
| PBIST7 | 0034 0160h |
| PBIST8 | 0035 0160h |
| WKUP_PBIST0 | 2B50 0160h |
| WKUP_PBIST1 | 2B50 1160h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RGS | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RDS | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| DWR | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PLS | RLS | |||||
| NONE | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:24 | RGS | R/W | 0h | RAM Group Select RGS Reset Source: mod_g_rst_n |
| 23:16 | RDS | R/W | 0h | Return Data select RDS Reset Source: mod_g_rst_n |
| 15:8 | DWR | R/W | 0h | Data Width Register DWR Reset Source: mod_g_rst_n |
| 7:6 | RESERVED | NONE | 0h | Reserved |
| 5:2 | PLS | R/W | 0h | Pipeline Latency Select Reset Source: mod_g_rst_n |
| 1:0 | RLS | R/W | 0h | RAM Latency Select Reset Source: mod_g_rst_n |