SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
FIFO Control Register
Notes:
Bits 4 and 5 can only be written to when EFR[4] = 1
Bits 0 to 3 can be changed only when the baud clock is not running (DLL and DLH set to 0)
Always make sure that the FIFO is empty when disabling or enabling the FIFO, or reset it if this can't be guaranteed.
See the Transmit FIFO Trigger section of the device TRM for FCR[5:4] setting restriction when SCR[6]=1
See the Recieve FIFO Trigger section of the device TRM for FCR[7:6] setting restriction when SCR[7]=1
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| Instance Name | Physical Address |
|---|---|
| UART0 | 0280 0008h |
| UART1 | 0281 0008h |
| UART2 | 0282 0008h |
| UART3 | 0283 0008h |
| UART4 | 0284 0008h |
| UART5 | 0285 0008h |
| UART6 | 0286 0008h |
| WKUP_UART0 | 2B30 0008h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RX_FIFO_TRIG | TX_FIFO_TRIG | DMA_MODE | TX_FIFO_CLEAR | RX_FIFO_CLEAR | FIFO_EN | ||
| W | W | W | W | W | W | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED_24 | R | 0h | |
| 7:6 | RX_FIFO_TRIG | W | 0h | Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If SCR[7] = 0 and TLR[7:4] != 0000, RX_FIFO_TRIG is not considered. If SCR[7]=1, RX_FIFO_TRIG is 2 LSB of the trigger level [1-63 on 6 bits] with the granularity 1. Reset Source: mod_g_arstn |
| 5:4 | TX_FIFO_TRIG | W | 0h | Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If SCR[6] = 0 and TLR[3:0] != 0000, TX_FIFO_TRIG is not considered. If SCR[6]=1, TX_FIFO_TRIG is 2 LSB of the trigger level [1-63 on 6 bits] with the granularity 1 Reset Source: mod_g_arstn |
| 3 | DMA_MODE | W | 0h | This register is considered if SCR[0] = 0. 0 DMA_MODE 0 (No DMA)
1 DMA_MODE 1 (UART_nDMA_REQ[0] in TX,
UART_nDMA_REQ[1] in RX) |
| 2 | TX_FIFO_CLEAR | W | 0h | 0 No change
1 Clears the transmit FIFO and resets its
counter logic to zero. Returns to zero
after clearing FIFO. |
| 1 | RX_FIFO_CLEAR | W | 0h | 0 No change
1 Clears the receive FIFO and resets its
counter logic to zero. Returns to zero
after clearing FIFO. |
| 0 | FIFO_EN | W | 0h | 0 Disables the transmit and receive FIFOs.
The transmit and receive holding registers
are one byte FIFOs.
1 : Enables the transmit and receive
FIFOs.The transmit and receive holding
registers are 64-bytes FIFOs. |