SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Trigger Level Register
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| Instance Name | Physical Address |
|---|---|
| UART0 | 0280 001Ch |
| UART1 | 0281 001Ch |
| UART2 | 0282 001Ch |
| UART3 | 0283 001Ch |
| UART4 | 0284 001Ch |
| UART5 | 0285 001Ch |
| UART6 | 0286 001Ch |
| WKUP_UART0 | 2B30 001Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RX_FIFO_TRIG_DMA | TX_FIFO_TRIG_DMA | ||||||
| R/W | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED | NONE | 0h | Reserved |
| 7:4 | RX_FIFO_TRIG_DMA | R/W | 0h | Receive FIFO trigger level Reset Source: mod_g_arstn |
| 3:0 | TX_FIFO_TRIG_DMA | R/W | 0h | Transmit FIFO trigger level Reset Source: mod_g_arstn |