SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
IrDA modes only. The frame lengths of received frames are written into the status FIFO. This information can be read by reading the SFREGL and SFREGH registers (i.e. these registers do not physically exist). The least significant bits are read from SFREGL and the most significant bits are read from SFREGH. Reading these registers does not alter the status FIFO read pointer. These registers should be read before the pointer is incremented by reading the SFLSR.
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| Instance Name | Physical Address |
|---|---|
| UART0 | 0280 0030h |
| UART1 | 0281 0030h |
| UART2 | 0282 0030h |
| UART3 | 0283 0030h |
| UART4 | 0284 0030h |
| UART5 | 0285 0030h |
| UART6 | 0286 0030h |
| WKUP_UART0 | 2B30 0030h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SFREGL | |||||||
| R | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED_24 | R | 0h | |
| 7:0 | SFREGL | R | 0h | LSB part of the frame length Reset Source: mod_g_arstn |