SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Note: Bit 4 enables the wake-up interrupt, but this interrupt is not mapped into the IIR register. Therefore, when an interrupt occurs and there is no interrupt pending in the IIR register, the SSR[1] bit must be checked. To clear the wake-up interrupt, bit SCR[4] must be reset to 0.
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| Instance Name | Physical Address |
|---|---|
| UART0 | 0280 0040h |
| UART1 | 0281 0040h |
| UART2 | 0282 0040h |
| UART3 | 0283 0040h |
| UART4 | 0284 0040h |
| UART5 | 0285 0040h |
| UART6 | 0286 0040h |
| WKUP_UART0 | 2B30 0040h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RX_TRIG_GRANU1 | TX_TRIG_GRANU1 | DSR_IT | RX_CTS_DSR_WAKE_UP_ENABLE | TX_EMPTY_CTL_IT | DMA_MODE_2 | DMA_MODE_CTL | |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED_24 | R | 0h | |
| 7 | RX_TRIG_GRANU1 | R/W | 0h | 0 DISABLES THE GRANULARITY OF 1 FOR TRIGGER
RX LEVEL.
1 ENABLES THE GRANULARITY OF 1 FOR TRIGGER RX
LEVEL. |
| 6 | TX_TRIG_GRANU1 | R/W | 0h | 0 DISABLES THE GRANULARITY OF 1 FOR TRIGGER
TX LEVEL.
1 Enables the granularity of 1 for trigger TX
level. |
| 5 | DSR_IT | R/W | 0h | 0 DISABLES DSR* INTERRUPT. 1 ENABLES DSR* INTERRUPT. |
| 4 | RX_CTS_DSR_WAKE_UP_ENABLE | R/W | 0h | 0 DISABLES THE WAKE UP INTERRUPT AND CLEARS
SSR[1].
1 Waits for a falling edge of pins RX, CTS*
or DSR* to generate an interrupt |
| 3 | TX_EMPTY_CTL_IT | R/W | 0h | 0 Normal mode for THR interrupt (See UART
mode interrupts table).
1 THE THR INTERRUPT IS GENERATED WHEN TX FIFO
AND TX SHIFT REGISTER ARE EMPTY. |
| 2:1 | DMA_MODE_2 | R/W | 0h | Used to specify the DMA mode valid if SCR[0] = 1 0 DMA mode 0 (no DMA)
1 DMA mode 1 (UART_nDMA_REQ[0] in TX,
UART_nDMA_REQ[1] in RX)
2 DMA mode 2 (UART_nDMA_REQ[0] in RX)
3 DMA mode 3 (UART_nDMA_REQ[0] in TX) |
| 0 | DMA_MODE_CTL | R/W | 0h | 0 The DMA_MODE is set with FCR[3] 1 The DMA_MODE is set with SCR[2:1] |