SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Note: Bit 1 is reset only when SCR[4] is reset to 0.
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| Instance Name | Physical Address |
|---|---|
| UART0 | 0280 0044h |
| UART1 | 0281 0044h |
| UART2 | 0282 0044h |
| UART3 | 0283 0044h |
| UART4 | 0284 0044h |
| UART5 | 0285 0044h |
| UART6 | 0286 0044h |
| WKUP_UART0 | 2B30 0044h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DMA_COUNTER_RST | RX_CTS_DSR_WAKE_UP_STS | TX_FIFO_FULL | ||||
| R | R/W | R | R | ||||
| 0h | 1h | 0h | 0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED_24 | R | 0h | |
| 7:3 | RESERVED | R | 0h | |
| 2 | DMA_COUNTER_RST | R/W | 1h | 0 The DMA counter will not be reset if the
corresponding FIFO is reset (via FCR[1] or
FCR[2])
1 The DMA counter will be reset if
corresponding FIFO is reset (via FCR[1] or
FCR[2]) |
| 1 | RX_CTS_DSR_WAKE_UP_STS | R | 0h | 0 No falling edge event on RX, CTS* and DSR* 1 A falling edge occurred on RX, CTS* or DSR* |
| 0 | TX_FIFO_FULL | R | 0h | 0 TX FIFO is not full 1 TX FIFO is full. |