SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Enables RX/TX FIFOs empty corresponding interrupts.
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| Instance Name | Physical Address |
|---|---|
| UART0 | 0280 006Ch |
| UART1 | 0281 006Ch |
| UART2 | 0282 006Ch |
| UART3 | 0283 006Ch |
| UART4 | 0284 006Ch |
| UART5 | 0285 006Ch |
| UART6 | 0286 006Ch |
| WKUP_UART0 | 2B30 006Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED1 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED1 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED1 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RHR_IT_DIS | EN_TXFIFO_EMPTY | EN_RXFIFO_EMPTY | ||||
| R | R/W | R/W | R/W | ||||
| 0h | 0h | 0h | 0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED1 | R | 0h | |
| 7:3 | RESERVED | R | 0h | |
| 2 | RHR_IT_DIS | R/W | 0h | 0 Enables the RHR interrupt. 1 Disables the RHR interrupt. |
| 1 | EN_TXFIFO_EMPTY | R/W | 0h | Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt. Reset Source: mod_g_arstn |
| 0 | EN_RXFIFO_EMPTY | R/W | 0h | Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt. Reset Source: mod_g_arstn |