SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Mode definition register 4
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| Instance Name | Physical Address |
|---|---|
| UART0 | 0280 0088h |
| UART1 | 0281 0088h |
| UART2 | 0282 0088h |
| UART3 | 0283 0088h |
| UART4 | 0284 0088h |
| UART5 | 0285 0088h |
| UART6 | 0286 0088h |
| WKUP_UART0 | 2B30 0088h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED1 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED1 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED1 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | MODE9 | FREQ_SEL_H | MODE | ||||
| R | R/W | R/W | R/W | ||||
| 0h | 0h | 0h | 0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED1 | R | 0h | |
| 7 | RESERVED | R | 0h | |
| 6 | MODE9 | R/W | 0h | 9-bit character length. When '1', overrides character length setting in LCR Reset Source: mod_g_arstn |
| 5:3 | FREQ_SEL_H | R/W | 0h | Upper 3 bits of FREQ_SEL register for higher division values, as required for example for FI/Di in ISO7816 mode Reset Source: mod_g_arstn |
| 2:0 | MODE | R/W | 0h | New modes [when set, overrides MDR1 modes] 0 disabled (no override) 1 reserved 2 Synchronous mode with external clock 3 Synchronous mode with generated clock 4 ISO 7816 mode T=0 5 ISO 7816 mode T=1 6 reserved 7 reserved |