SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Extended Receive Holding Register
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| Instance Name | Physical Address |
|---|---|
| UART0 | 0280 00A4h |
| UART1 | 0281 00A4h |
| UART2 | 0282 00A4h |
| UART3 | 0283 00A4h |
| UART4 | 0284 00A4h |
| UART5 | 0285 00A4h |
| UART6 | 0286 00A4h |
| WKUP_UART0 | 2B30 00A4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | ERHR | ||||||
| R | R | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ERHR | |||||||
| R | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:9 | RESERVED | R | 0h | |
| 8:0 | ERHR | R | 0h | Extended Receive Holding Register - allows accessing the full 9bit RHR Reset Source: mod_g_arstn |