SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
U3 Root Hub Debug Register
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| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 D800h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_1 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_1 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_1 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED_1 | TPCFG_TOUT_CTRL | RESERVED_0_2 | |||||
| R | R/W | R | |||||
| 0h | 0h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:4 | RESERVED_1 | R | 0h | Reserved_1 |
| 3 | TPCFG_TOUT_CTRL | R/W | 0h | tpcfg_tout_ctrl This bit controls the USB 3.0 port configuration timeout duration. - 1: The port configuration timeout counter resets when the link is not in U0. - 0: The port configuration timeout counter does not reset if the link enters recovery or exits U0. Reset Source: rst_mod_g_rst_n |
| 2:0 | RESERVED_0_2 | R | 0h | Reserved_0_2 |