SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
| IN Interrupt | Connected To |
|---|---|
|
R5FSS0_CORE0_INTR_IN_0 |
MAIN_CTRL_MMR0_IPC_SET16_IPC_SET_IPCFG_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_3 |
EPWM0_EPWM_ETINT_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_4 |
R5FSS0_CORE0_EXP_INTR_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_5 |
R5FSS0_COMMON0_COMMRX_LEVEL_0_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_6 |
R5FSS0_COMMON0_COMMTX_LEVEL_0_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_7 |
SA3_SS0_INTAGGR_0_INTAGGR_VINTR_OUT_7 |
|
R5FSS0_CORE0_INTR_IN_8 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_168 |
|
R5FSS0_CORE0_INTR_IN_9 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_169 |
|
R5FSS0_CORE0_INTR_IN_10 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_170 |
|
R5FSS0_CORE0_INTR_IN_11 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_171 |
|
R5FSS0_CORE0_INTR_IN_12 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_172 |
|
R5FSS0_CORE0_INTR_IN_13 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_173 |
|
R5FSS0_CORE0_INTR_IN_14 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_174 |
|
R5FSS0_CORE0_INTR_IN_15 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_175 |
|
R5FSS0_CORE0_INTR_IN_16 |
SA3_SS0_SA_UL_0_SA_UL_PKA_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_17 |
SA3_SS0_SA_UL_0_SA_UL_TRNG_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_22 |
TIMER6_INTR_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_23 |
TIMER7_INTR_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_24 |
TIMER0_INTR_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_25 |
TIMER1_INTR_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_26 |
TIMER2_INTR_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_27 |
TIMER3_INTR_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_28 |
TIMER4_INTR_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_29 |
TIMER5_INTR_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_30 |
RTI0_INTR_WWD_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_31 |
WKUP_CBASS_SAFE1_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_32 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_16 |
|
R5FSS0_CORE0_INTR_IN_33 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_17 |
|
R5FSS0_CORE0_INTR_IN_34 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_18 |
|
R5FSS0_CORE0_INTR_IN_35 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_19 |
|
R5FSS0_CORE0_INTR_IN_36 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_20 |
|
R5FSS0_CORE0_INTR_IN_37 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_21 |
|
R5FSS0_CORE0_INTR_IN_38 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_22 |
|
R5FSS0_CORE0_INTR_IN_39 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_23 |
|
R5FSS0_CORE0_INTR_IN_40 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_24 |
|
R5FSS0_CORE0_INTR_IN_41 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_25 |
|
R5FSS0_CORE0_INTR_IN_42 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_26 |
|
R5FSS0_CORE0_INTR_IN_43 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_27 |
|
R5FSS0_CORE0_INTR_IN_44 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_28 |
|
R5FSS0_CORE0_INTR_IN_45 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_29 |
|
R5FSS0_CORE0_INTR_IN_46 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_30 |
|
R5FSS0_CORE0_INTR_IN_47 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_31 |
|
R5FSS0_CORE0_INTR_IN_48 |
CPSW0_CPTS_COMP_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_50 |
AASRC0_INFIFO_LEVEL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_51 |
AASRC0_INGROUP_LEVEL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_52 |
AASRC0_OUTFIFO_LEVEL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_53 |
AASRC0_OUTGROUP_LEVEL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_54 |
AASRC0_ERR_LEVEL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_55 |
AASRC1_INFIFO_LEVEL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_56 |
AASRC1_INGROUP_LEVEL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_57 |
AASRC1_OUTFIFO_LEVEL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_58 |
AASRC1_OUTGROUP_LEVEL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_59 |
AASRC1_ERR_LEVEL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_60 |
MLB0_MLBSS_MLB_INT_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_61 |
MLB0_MLBSS_MLB_AHB_INT_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_62 |
MLB0_MLBSS_MLB_AHB_INT_OUT_1 |
|
R5FSS0_CORE0_INTR_IN_64 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_152 |
|
R5FSS0_CORE0_INTR_IN_65 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_153 |
|
R5FSS0_CORE0_INTR_IN_66 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_154 |
|
R5FSS0_CORE0_INTR_IN_67 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_155 |
|
R5FSS0_CORE0_INTR_IN_68 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_156 |
|
R5FSS0_CORE0_INTR_IN_69 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_157 |
|
R5FSS0_CORE0_INTR_IN_70 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_158 |
|
R5FSS0_CORE0_INTR_IN_71 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_159 |
|
R5FSS0_CORE0_INTR_IN_72 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_160 |
|
R5FSS0_CORE0_INTR_IN_73 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_161 |
|
R5FSS0_CORE0_INTR_IN_74 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_162 |
|
R5FSS0_CORE0_INTR_IN_75 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_163 |
|
R5FSS0_CORE0_INTR_IN_76 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_164 |
|
R5FSS0_CORE0_INTR_IN_77 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_165 |
|
R5FSS0_CORE0_INTR_IN_78 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_166 |
|
R5FSS0_CORE0_INTR_IN_79 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_167 |
|
R5FSS0_CORE0_INTR_IN_80 |
EPWM0_EPWM_TRIPZINT_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_81 |
EPWM1_EPWM_TRIPZINT_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_82 |
EPWM2_EPWM_TRIPZINT_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_83 |
ECAP0_ECAP_INT_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_84 |
ECAP1_ECAP_INT_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_85 |
ECAP2_ECAP_INT_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_86 |
ECAP3_ECAP_INT_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_87 |
ECAP4_ECAP_INT_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_88 |
ECAP5_ECAP_INT_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_90 |
RL2_0_ERR_LVL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_91 |
RL2_2_ERR_LVL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_92 |
RL2_3_ERR_LVL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_93 |
R5FSS0_CORE1_PMU_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_94 |
R5FSS0_CORE0_PMU_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_95 |
R5FSS0_CORE0_VALFIQ_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_96 |
R5FSS0_CORE0_VALIRQ_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_97 |
WKUP_RTCSS0_RTC_EVENT_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_98 |
EFUSE0_EFC_ERROR_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_100 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_16 |
|
R5FSS0_CORE0_INTR_IN_101 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_17 |
|
R5FSS0_CORE0_INTR_IN_102 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_18 |
|
R5FSS0_CORE0_INTR_IN_103 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_19 |
|
R5FSS0_CORE0_INTR_IN_104 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_20 |
|
R5FSS0_CORE0_INTR_IN_105 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_21 |
|
R5FSS0_CORE0_INTR_IN_106 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_22 |
|
R5FSS0_CORE0_INTR_IN_107 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_23 |
|
R5FSS0_CORE0_INTR_IN_108 |
MCU_DCC0_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_109 |
DCC0_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_109 |
DCC1_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_109 |
DCC2_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_109 |
DCC3_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_109 |
DCC4_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_109 |
DCC5_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_109 |
DCC6_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_109 |
DCC7_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_109 |
DCC8_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_113 |
PBIST0_DFT_PBIST_CPU_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_113 |
PBIST5_DFT_PBIST_CPU_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_113 |
PBIST6_DFT_PBIST_CPU_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_113 |
PBIST7_DFT_PBIST_CPU_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_113 |
PBIST8_DFT_PBIST_CPU_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_113 |
PBIST1_DFT_PBIST_CPU_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_113 |
PBIST2_DFT_PBIST_CPU_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_113 |
C7X256V0_CLEC_DFT_PBIST_CPU_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_113 |
C7X256V1_CLEC_DFT_PBIST_CPU_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_113 |
PBIST3_DFT_PBIST_CPU_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_113 |
PBIST4_DFT_PBIST_CPU_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_114 |
WKUP_PBIST0_DFT_PBIST_CPU_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_114 |
WKUP_PBIST1_DFT_PBIST_CPU_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_119 |
MCRC64_0_INT_MCRC_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_120 |
MCASP0_REC_INTR_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_121 |
MCASP0_XMIT_INTR_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_122 |
MCASP1_REC_INTR_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_123 |
MCASP1_XMIT_INTR_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_124 |
MCASP2_REC_INTR_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_125 |
MCASP2_XMIT_INTR_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_126 |
MCASP3_REC_INTR_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_127 |
MCASP3_XMIT_INTR_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_128 |
MAIN_CTRL_MMR0_ACCESS_ERR_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_128 |
WKUP_CTRL_MMR0_ACCESS_ERR_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_128 |
PADCFG_CTRL0_ACCESS_ERR_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_128 |
MCU_CTRL_MMR0_ACCESS_ERR_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_128 |
MCU_PADCFG_CTRL0_ACCESS_ERR_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_130 |
MCASP4_REC_INTR_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_131 |
MCASP4_XMIT_INTR_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_134 |
CPSW0_EVNT_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_135 |
CPSW0_MDIO_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_136 |
CPSW0_STAT_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_137 |
MCU_DCC1_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_140 |
WKUP_ESM0_ESM_INT_CFG_LVL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_141 |
WKUP_ESM0_ESM_INT_HI_LVL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_142 |
WKUP_ESM0_ESM_INT_LOW_LVL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_145 |
WKUP_PSC0_PSC_ALLINT_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_146 |
MAIN_PSC0_PSC_ALLINT_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_147 |
CBASS0_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_147 |
CBASS_INFRA1_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_147 |
WKUP_CBASS_SAFE1_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_147 |
CBASS_MCASP0_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_147 |
CBASS_MEM0_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_147 |
CBASS_DBG0_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_147 |
CBASS_CENTRAL2_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_147 |
AM275_MAIN_IPCSS_CBASS0_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_147 |
CBASS_MISC_PERI0_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_147 |
WKUP_CBASS0_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_151 |
ADC0_GEN_LEVEL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_153 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_176 |
|
R5FSS0_CORE0_INTR_IN_154 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_177 |
|
R5FSS0_CORE0_INTR_IN_155 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_178 |
|
R5FSS0_CORE0_INTR_IN_156 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_179 |
|
R5FSS0_CORE0_INTR_IN_157 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_180 |
|
R5FSS0_CORE0_INTR_IN_158 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_181 |
|
R5FSS0_CORE0_INTR_IN_159 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_182 |
|
R5FSS0_CORE0_INTR_IN_160 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_183 |
|
R5FSS0_CORE0_INTR_IN_161 |
MMCSD0_EMMCSDSS_INTR_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_167 |
ESM0_ESM_INT_CFG_LVL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_168 |
ESM0_ESM_INT_HI_LVL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_169 |
ESM0_ESM_INT_LOW_LVL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_171 |
FSS0_OSPI0_LVL_INTR_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_172 |
FSS0_FSAS_FOTA_STAT_INTR_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_173 |
FSS0_FSAS_FOTA_STAT_ERR_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_174 |
FSS0_OTFA_INTR_ERR_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_175 |
R5FSS0_CORE0_CTI_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_176 |
R5FSS0_CORE1_CTI_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_177 |
DDPA0_DDPA_INTR_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_178 |
FSS1_OSPI_0_OSPI_LVL_INTR_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_179 |
FSS1_HYPERBUS1P0_0_HPB_INTR_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_180 |
FSS1_FSAS_0_OTFA_INTR_ERR_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_181 |
FSS1_FSAS_0_ECC_INTR_ERR_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_182 |
FSS0_FSAS_ECC_INTR_ERR_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_183 |
WKUP_VTM0_THERM_LVL_GT_TH1_INTR_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_184 |
WKUP_VTM0_THERM_LVL_GT_TH2_INTR_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_185 |
WKUP_VTM0_THERM_LVL_LT_TH0_INTR_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_186 |
MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_187 |
MCAN2_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_188 |
MCAN3_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_189 |
MCAN4_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_190 |
WKUP_I2C0_POINTRPEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_193 |
I2C0_POINTRPEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_194 |
I2C1_POINTRPEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_195 |
I2C2_POINTRPEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_196 |
I2C3_POINTRPEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_197 |
I2C4_POINTRPEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_198 |
I2C5_POINTRPEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_199 |
I2C6_POINTRPEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_201 |
DEBUGSS0_AQCMPINTR_LEVEL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_202 |
DEBUGSS0_CTM_LEVEL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_203 |
PINFUNCTION_EXTINTNIN_EXTINTN_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_204 |
MCSPI0_INTR_SPI_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_205 |
MCSPI1_INTR_SPI_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_206 |
MCSPI2_INTR_SPI_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_207 |
MCSPI3_INTR_SPI_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_208 |
MCSPI4_INTR_SPI_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_210 |
UART0_USART_IRQ_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_211 |
UART1_USART_IRQ_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_212 |
UART2_USART_IRQ_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_213 |
UART3_USART_IRQ_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_214 |
UART4_USART_IRQ_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_215 |
UART5_USART_IRQ_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_216 |
UART6_USART_IRQ_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_219 |
WKUP_UART0_USART_IRQ_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_220 |
USB0_IRQ_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_221 |
USB0_IRQ_OUT_1 |
|
R5FSS0_CORE0_INTR_IN_222 |
USB0_IRQ_OUT_2 |
|
R5FSS0_CORE0_INTR_IN_223 |
USB0_IRQ_OUT_3 |
|
R5FSS0_CORE0_INTR_IN_224 |
USB0_IRQ_OUT_4 |
|
R5FSS0_CORE0_INTR_IN_225 |
USB0_IRQ_OUT_5 |
|
R5FSS0_CORE0_INTR_IN_226 |
USB0_IRQ_OUT_6 |
|
R5FSS0_CORE0_INTR_IN_227 |
USB0_IRQ_OUT_7 |
|
R5FSS0_CORE0_INTR_IN_228 |
USB0_MISC_LEVEL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_229 |
MCAN1_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_230 |
MCAN0_MCANSS_MCAN_LVL_INT_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_231 |
MCAN0_MCANSS_MCAN_LVL_INT_OUT_1 |
|
R5FSS0_CORE0_INTR_IN_232 |
MCAN1_MCANSS_MCAN_LVL_INT_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_233 |
MCAN1_MCANSS_MCAN_LVL_INT_OUT_1 |
|
R5FSS0_CORE0_INTR_IN_234 |
MCAN2_MCANSS_MCAN_LVL_INT_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_235 |
MCAN2_MCANSS_MCAN_LVL_INT_OUT_1 |
|
R5FSS0_CORE0_INTR_IN_236 |
MCAN3_MCANSS_MCAN_LVL_INT_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_237 |
MCAN3_MCANSS_MCAN_LVL_INT_OUT_1 |
|
R5FSS0_CORE0_INTR_IN_238 |
MCAN4_MCANSS_MCAN_LVL_INT_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_239 |
MCAN4_MCANSS_MCAN_LVL_INT_OUT_1 |
|
R5FSS0_CORE0_INTR_IN_240 |
MAILBOX0_MAILBOX_CLUSTER_0_MAILBOX_CLUSTER_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_241 |
MAILBOX0_MAILBOX_CLUSTER_1_MAILBOX_CLUSTER_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_242 |
MAILBOX0_MAILBOX_CLUSTER_3_MAILBOX_CLUSTER_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_243 |
MAILBOX0_MAILBOX_CLUSTER_5_MAILBOX_CLUSTER_PEND_OUT_1 |
|
R5FSS0_CORE0_INTR_IN_248 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_249 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_1 |
|
R5FSS0_CORE0_INTR_IN_250 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_2 |
|
R5FSS0_CORE0_INTR_IN_251 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_3 |
|
R5FSS0_CORE0_INTR_IN_252 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_4 |
|
R5FSS0_CORE0_INTR_IN_253 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_5 |
|
R5FSS0_CORE0_INTR_IN_254 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_6 |
|
R5FSS0_CORE0_INTR_IN_255 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_7 |
|
R5FSS0_CORE0_INTR_IN_256 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_257 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_1 |
|
R5FSS0_CORE0_INTR_IN_258 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_2 |
|
R5FSS0_CORE0_INTR_IN_259 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_3 |
|
R5FSS0_CORE0_INTR_IN_260 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_4 |
|
R5FSS0_CORE0_INTR_IN_261 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_5 |
|
R5FSS0_CORE0_INTR_IN_262 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_6 |
|
R5FSS0_CORE0_INTR_IN_263 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_7 |
|
R5FSS0_CORE0_INTR_IN_264 |
TIMER8_INTR_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_265 |
TIMER9_INTR_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_266 |
TIMER10_INTR_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_267 |
TIMER11_INTR_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_268 |
TIMER12_INTR_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_269 |
TIMER13_INTR_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_270 |
TIMER14_INTR_PEND_OUT_0 |
|
R5FSS0_CORE0_INTR_IN_271 |
TIMER15_INTR_PEND_OUT_0 |
| IN Interrupt | Connected To |
|---|---|
|
R5FSS0_CORE1_INTR_IN_0 |
MAIN_CTRL_MMR0_IPC_SET17_IPC_SET_IPCFG_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_4 |
R5FSS0_CORE1_EXP_INTR_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_5 |
R5FSS0_COMMON0_COMMRX_LEVEL_1_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_6 |
R5FSS0_COMMON0_COMMTX_LEVEL_1_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_7 |
SA3_SS0_INTAGGR_0_INTAGGR_VINTR_OUT_7 |
|
R5FSS0_CORE1_INTR_IN_8 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_168 |
|
R5FSS0_CORE1_INTR_IN_9 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_169 |
|
R5FSS0_CORE1_INTR_IN_10 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_170 |
|
R5FSS0_CORE1_INTR_IN_11 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_171 |
|
R5FSS0_CORE1_INTR_IN_12 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_172 |
|
R5FSS0_CORE1_INTR_IN_13 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_173 |
|
R5FSS0_CORE1_INTR_IN_14 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_174 |
|
R5FSS0_CORE1_INTR_IN_15 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_175 |
|
R5FSS0_CORE1_INTR_IN_16 |
SA3_SS0_SA_UL_0_SA_UL_PKA_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_17 |
SA3_SS0_SA_UL_0_SA_UL_TRNG_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_22 |
TIMER6_INTR_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_23 |
TIMER7_INTR_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_24 |
TIMER0_INTR_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_25 |
TIMER1_INTR_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_26 |
TIMER2_INTR_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_27 |
TIMER3_INTR_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_28 |
TIMER4_INTR_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_29 |
TIMER5_INTR_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_30 |
RTI1_INTR_WWD_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_31 |
WKUP_CBASS_SAFE1_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_32 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_16 |
|
R5FSS0_CORE1_INTR_IN_33 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_17 |
|
R5FSS0_CORE1_INTR_IN_34 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_18 |
|
R5FSS0_CORE1_INTR_IN_35 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_19 |
|
R5FSS0_CORE1_INTR_IN_36 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_20 |
|
R5FSS0_CORE1_INTR_IN_37 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_21 |
|
R5FSS0_CORE1_INTR_IN_38 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_22 |
|
R5FSS0_CORE1_INTR_IN_39 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_23 |
|
R5FSS0_CORE1_INTR_IN_40 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_24 |
|
R5FSS0_CORE1_INTR_IN_41 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_25 |
|
R5FSS0_CORE1_INTR_IN_42 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_26 |
|
R5FSS0_CORE1_INTR_IN_43 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_27 |
|
R5FSS0_CORE1_INTR_IN_44 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_28 |
|
R5FSS0_CORE1_INTR_IN_45 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_29 |
|
R5FSS0_CORE1_INTR_IN_46 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_30 |
|
R5FSS0_CORE1_INTR_IN_47 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_31 |
|
R5FSS0_CORE1_INTR_IN_48 |
CPSW0_CPTS_COMP_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_49 |
RL2_0_ERR_LVL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_50 |
AASRC0_INFIFO_LEVEL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_51 |
AASRC0_INGROUP_LEVEL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_52 |
AASRC0_OUTFIFO_LEVEL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_53 |
AASRC0_OUTGROUP_LEVEL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_54 |
AASRC0_ERR_LEVEL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_55 |
AASRC1_INFIFO_LEVEL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_56 |
AASRC1_INGROUP_LEVEL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_57 |
AASRC1_OUTFIFO_LEVEL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_58 |
AASRC1_OUTGROUP_LEVEL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_59 |
AASRC1_ERR_LEVEL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_60 |
MLB0_MLBSS_MLB_INT_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_61 |
MLB0_MLBSS_MLB_AHB_INT_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_62 |
MLB0_MLBSS_MLB_AHB_INT_OUT_1 |
|
R5FSS0_CORE1_INTR_IN_64 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_152 |
|
R5FSS0_CORE1_INTR_IN_65 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_153 |
|
R5FSS0_CORE1_INTR_IN_66 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_154 |
|
R5FSS0_CORE1_INTR_IN_67 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_155 |
|
R5FSS0_CORE1_INTR_IN_68 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_156 |
|
R5FSS0_CORE1_INTR_IN_69 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_157 |
|
R5FSS0_CORE1_INTR_IN_70 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_158 |
|
R5FSS0_CORE1_INTR_IN_71 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_159 |
|
R5FSS0_CORE1_INTR_IN_72 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_160 |
|
R5FSS0_CORE1_INTR_IN_73 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_161 |
|
R5FSS0_CORE1_INTR_IN_74 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_162 |
|
R5FSS0_CORE1_INTR_IN_75 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_163 |
|
R5FSS0_CORE1_INTR_IN_76 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_164 |
|
R5FSS0_CORE1_INTR_IN_77 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_165 |
|
R5FSS0_CORE1_INTR_IN_78 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_166 |
|
R5FSS0_CORE1_INTR_IN_79 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_167 |
|
R5FSS0_CORE1_INTR_IN_80 |
EPWM0_EPWM_TRIPZINT_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_81 |
EPWM1_EPWM_TRIPZINT_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_82 |
EPWM2_EPWM_TRIPZINT_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_83 |
ECAP0_ECAP_INT_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_84 |
ECAP1_ECAP_INT_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_85 |
ECAP2_ECAP_INT_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_86 |
ECAP3_ECAP_INT_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_87 |
ECAP4_ECAP_INT_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_88 |
ECAP5_ECAP_INT_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_90 |
RL2_0_ERR_LVL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_91 |
RL2_2_ERR_LVL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_92 |
RL2_3_ERR_LVL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_93 |
R5FSS0_CORE1_PMU_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_94 |
R5FSS0_CORE0_PMU_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_95 |
R5FSS0_CORE1_VALFIQ_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_96 |
R5FSS0_CORE1_VALIRQ_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_97 |
WKUP_RTCSS0_RTC_EVENT_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_98 |
EFUSE0_EFC_ERROR_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_100 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_16 |
|
R5FSS0_CORE1_INTR_IN_101 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_17 |
|
R5FSS0_CORE1_INTR_IN_102 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_18 |
|
R5FSS0_CORE1_INTR_IN_103 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_19 |
|
R5FSS0_CORE1_INTR_IN_104 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_20 |
|
R5FSS0_CORE1_INTR_IN_105 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_21 |
|
R5FSS0_CORE1_INTR_IN_106 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_22 |
|
R5FSS0_CORE1_INTR_IN_107 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_23 |
|
R5FSS0_CORE1_INTR_IN_108 |
MCU_DCC0_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_109 |
DCC0_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_109 |
DCC1_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_109 |
DCC2_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_109 |
DCC3_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_109 |
DCC4_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_109 |
DCC5_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_109 |
DCC6_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_109 |
DCC7_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_109 |
DCC8_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_113 |
PBIST0_DFT_PBIST_CPU_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_113 |
PBIST5_DFT_PBIST_CPU_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_113 |
PBIST6_DFT_PBIST_CPU_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_113 |
PBIST7_DFT_PBIST_CPU_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_113 |
PBIST8_DFT_PBIST_CPU_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_113 |
PBIST1_DFT_PBIST_CPU_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_113 |
PBIST2_DFT_PBIST_CPU_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_113 |
C7X256V0_CLEC_DFT_PBIST_CPU_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_113 |
C7X256V1_CLEC_DFT_PBIST_CPU_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_113 |
PBIST3_DFT_PBIST_CPU_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_113 |
PBIST4_DFT_PBIST_CPU_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_114 |
WKUP_PBIST0_DFT_PBIST_CPU_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_114 |
WKUP_PBIST1_DFT_PBIST_CPU_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_119 |
MCRC64_0_INT_MCRC_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_120 |
MCASP0_REC_INTR_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_121 |
MCASP0_XMIT_INTR_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_122 |
MCASP1_REC_INTR_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_123 |
MCASP1_XMIT_INTR_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_124 |
MCASP2_REC_INTR_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_125 |
MCASP2_XMIT_INTR_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_126 |
MCASP3_REC_INTR_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_127 |
MCASP3_XMIT_INTR_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_128 |
MAIN_CTRL_MMR0_ACCESS_ERR_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_128 |
WKUP_CTRL_MMR0_ACCESS_ERR_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_128 |
PADCFG_CTRL0_ACCESS_ERR_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_128 |
MCU_CTRL_MMR0_ACCESS_ERR_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_128 |
MCU_PADCFG_CTRL0_ACCESS_ERR_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_130 |
MCASP4_REC_INTR_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_131 |
MCASP4_XMIT_INTR_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_134 |
CPSW0_EVNT_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_135 |
CPSW0_MDIO_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_136 |
CPSW0_STAT_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_137 |
MCU_DCC1_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_140 |
WKUP_ESM0_ESM_INT_CFG_LVL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_141 |
WKUP_ESM0_ESM_INT_HI_LVL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_142 |
WKUP_ESM0_ESM_INT_LOW_LVL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_145 |
WKUP_PSC0_PSC_ALLINT_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_146 |
MAIN_PSC0_PSC_ALLINT_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_147 |
CBASS0_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_147 |
CBASS_INFRA1_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_147 |
WKUP_CBASS_SAFE1_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_147 |
CBASS_MCASP0_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_147 |
CBASS_MEM0_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_147 |
CBASS_DBG0_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_147 |
CBASS_CENTRAL2_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_147 |
AM275_MAIN_IPCSS_CBASS0_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_147 |
CBASS_MISC_PERI0_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_147 |
WKUP_CBASS0_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_151 |
ADC0_GEN_LEVEL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_153 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_176 |
|
R5FSS0_CORE1_INTR_IN_154 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_177 |
|
R5FSS0_CORE1_INTR_IN_155 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_178 |
|
R5FSS0_CORE1_INTR_IN_156 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_179 |
|
R5FSS0_CORE1_INTR_IN_157 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_180 |
|
R5FSS0_CORE1_INTR_IN_158 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_181 |
|
R5FSS0_CORE1_INTR_IN_159 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_182 |
|
R5FSS0_CORE1_INTR_IN_160 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_183 |
|
R5FSS0_CORE1_INTR_IN_161 |
MMCSD0_EMMCSDSS_INTR_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_167 |
ESM0_ESM_INT_CFG_LVL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_168 |
ESM0_ESM_INT_HI_LVL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_169 |
ESM0_ESM_INT_LOW_LVL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_171 |
FSS0_OSPI0_LVL_INTR_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_172 |
FSS0_FSAS_FOTA_STAT_INTR_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_173 |
FSS0_FSAS_FOTA_STAT_ERR_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_174 |
FSS0_OTFA_INTR_ERR_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_175 |
R5FSS0_CORE0_CTI_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_176 |
R5FSS0_CORE1_CTI_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_177 |
DDPA0_DDPA_INTR_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_178 |
FSS1_OSPI_0_OSPI_LVL_INTR_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_179 |
FSS1_HYPERBUS1P0_0_HPB_INTR_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_180 |
FSS1_FSAS_0_OTFA_INTR_ERR_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_181 |
FSS1_FSAS_0_ECC_INTR_ERR_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_182 |
FSS0_FSAS_ECC_INTR_ERR_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_183 |
WKUP_VTM0_THERM_LVL_GT_TH1_INTR_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_184 |
WKUP_VTM0_THERM_LVL_GT_TH2_INTR_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_185 |
WKUP_VTM0_THERM_LVL_LT_TH0_INTR_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_186 |
MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_187 |
MCAN2_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_188 |
MCAN3_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_189 |
MCAN4_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_190 |
WKUP_I2C0_POINTRPEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_193 |
I2C0_POINTRPEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_194 |
I2C1_POINTRPEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_195 |
I2C2_POINTRPEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_196 |
I2C3_POINTRPEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_197 |
I2C4_POINTRPEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_198 |
I2C5_POINTRPEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_199 |
I2C6_POINTRPEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_201 |
DEBUGSS0_AQCMPINTR_LEVEL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_202 |
DEBUGSS0_CTM_LEVEL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_203 |
PINFUNCTION_EXTINTNIN_EXTINTN_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_204 |
MCSPI0_INTR_SPI_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_205 |
MCSPI1_INTR_SPI_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_206 |
MCSPI2_INTR_SPI_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_207 |
MCSPI3_INTR_SPI_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_208 |
MCSPI4_INTR_SPI_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_210 |
UART0_USART_IRQ_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_211 |
UART1_USART_IRQ_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_212 |
UART2_USART_IRQ_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_213 |
UART3_USART_IRQ_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_214 |
UART4_USART_IRQ_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_215 |
UART5_USART_IRQ_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_216 |
UART6_USART_IRQ_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_219 |
WKUP_UART0_USART_IRQ_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_220 |
USB0_IRQ_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_221 |
USB0_IRQ_OUT_1 |
|
R5FSS0_CORE1_INTR_IN_222 |
USB0_IRQ_OUT_2 |
|
R5FSS0_CORE1_INTR_IN_223 |
USB0_IRQ_OUT_3 |
|
R5FSS0_CORE1_INTR_IN_224 |
USB0_IRQ_OUT_4 |
|
R5FSS0_CORE1_INTR_IN_225 |
USB0_IRQ_OUT_5 |
|
R5FSS0_CORE1_INTR_IN_226 |
USB0_IRQ_OUT_6 |
|
R5FSS0_CORE1_INTR_IN_227 |
USB0_IRQ_OUT_7 |
|
R5FSS0_CORE1_INTR_IN_228 |
USB0_MISC_LEVEL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_229 |
MCAN1_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_230 |
MCAN0_MCANSS_MCAN_LVL_INT_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_231 |
MCAN0_MCANSS_MCAN_LVL_INT_OUT_1 |
|
R5FSS0_CORE1_INTR_IN_232 |
MCAN1_MCANSS_MCAN_LVL_INT_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_233 |
MCAN1_MCANSS_MCAN_LVL_INT_OUT_1 |
|
R5FSS0_CORE1_INTR_IN_234 |
MCAN2_MCANSS_MCAN_LVL_INT_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_235 |
MCAN2_MCANSS_MCAN_LVL_INT_OUT_1 |
|
R5FSS0_CORE1_INTR_IN_236 |
MCAN3_MCANSS_MCAN_LVL_INT_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_237 |
MCAN3_MCANSS_MCAN_LVL_INT_OUT_1 |
|
R5FSS0_CORE1_INTR_IN_238 |
MCAN4_MCANSS_MCAN_LVL_INT_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_239 |
MCAN4_MCANSS_MCAN_LVL_INT_OUT_1 |
|
R5FSS0_CORE1_INTR_IN_240 |
MAILBOX0_MAILBOX_CLUSTER_0_MAILBOX_CLUSTER_PEND_OUT_1 |
|
R5FSS0_CORE1_INTR_IN_241 |
MAILBOX0_MAILBOX_CLUSTER_2_MAILBOX_CLUSTER_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_242 |
MAILBOX0_MAILBOX_CLUSTER_3_MAILBOX_CLUSTER_PEND_OUT_1 |
|
R5FSS0_CORE1_INTR_IN_243 |
MAILBOX0_MAILBOX_CLUSTER_6_MAILBOX_CLUSTER_PEND_OUT_1 |
|
R5FSS0_CORE1_INTR_IN_248 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_249 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_1 |
|
R5FSS0_CORE1_INTR_IN_250 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_2 |
|
R5FSS0_CORE1_INTR_IN_251 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_3 |
|
R5FSS0_CORE1_INTR_IN_252 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_4 |
|
R5FSS0_CORE1_INTR_IN_253 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_5 |
|
R5FSS0_CORE1_INTR_IN_254 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_6 |
|
R5FSS0_CORE1_INTR_IN_255 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_7 |
|
R5FSS0_CORE1_INTR_IN_256 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_257 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_1 |
|
R5FSS0_CORE1_INTR_IN_258 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_2 |
|
R5FSS0_CORE1_INTR_IN_259 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_3 |
|
R5FSS0_CORE1_INTR_IN_260 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_4 |
|
R5FSS0_CORE1_INTR_IN_261 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_5 |
|
R5FSS0_CORE1_INTR_IN_262 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_6 |
|
R5FSS0_CORE1_INTR_IN_263 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_7 |
|
R5FSS0_CORE1_INTR_IN_264 |
TIMER8_INTR_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_265 |
TIMER9_INTR_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_266 |
TIMER10_INTR_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_267 |
TIMER11_INTR_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_268 |
TIMER12_INTR_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_269 |
TIMER13_INTR_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_270 |
TIMER14_INTR_PEND_OUT_0 |
|
R5FSS0_CORE1_INTR_IN_271 |
TIMER15_INTR_PEND_OUT_0 |
| IN Interrupt | Connected To |
|---|---|
|
R5FSS1_CORE0_INTR_IN_0 |
MAIN_CTRL_MMR0_IPC_SET18_IPC_SET_IPCFG_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_4 |
R5FSS1_CORE0_EXP_INTR_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_5 |
R5FSS1_COMMON0_COMMRX_LEVEL_0_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_6 |
R5FSS1_COMMON0_COMMTX_LEVEL_0_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_7 |
SA3_SS0_INTAGGR_0_INTAGGR_VINTR_OUT_7 |
|
R5FSS1_CORE0_INTR_IN_8 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_16 |
|
R5FSS1_CORE0_INTR_IN_9 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_17 |
|
R5FSS1_CORE0_INTR_IN_10 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_18 |
|
R5FSS1_CORE0_INTR_IN_11 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_19 |
|
R5FSS1_CORE0_INTR_IN_12 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_20 |
|
R5FSS1_CORE0_INTR_IN_13 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_21 |
|
R5FSS1_CORE0_INTR_IN_14 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_22 |
|
R5FSS1_CORE0_INTR_IN_15 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_23 |
|
R5FSS1_CORE0_INTR_IN_16 |
SA3_SS0_SA_UL_0_SA_UL_PKA_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_17 |
SA3_SS0_SA_UL_0_SA_UL_TRNG_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_22 |
TIMER6_INTR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_23 |
TIMER7_INTR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_24 |
TIMER0_INTR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_25 |
TIMER1_INTR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_26 |
TIMER2_INTR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_27 |
TIMER3_INTR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_28 |
TIMER4_INTR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_29 |
TIMER5_INTR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_30 |
RTI2_INTR_WWD_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_31 |
WKUP_CBASS_SAFE1_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_32 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_32 |
|
R5FSS1_CORE0_INTR_IN_33 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_33 |
|
R5FSS1_CORE0_INTR_IN_34 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_34 |
|
R5FSS1_CORE0_INTR_IN_35 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_35 |
|
R5FSS1_CORE0_INTR_IN_36 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_36 |
|
R5FSS1_CORE0_INTR_IN_37 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_37 |
|
R5FSS1_CORE0_INTR_IN_38 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_38 |
|
R5FSS1_CORE0_INTR_IN_39 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_39 |
|
R5FSS1_CORE0_INTR_IN_40 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_40 |
|
R5FSS1_CORE0_INTR_IN_41 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_41 |
|
R5FSS1_CORE0_INTR_IN_42 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_42 |
|
R5FSS1_CORE0_INTR_IN_43 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_43 |
|
R5FSS1_CORE0_INTR_IN_44 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_44 |
|
R5FSS1_CORE0_INTR_IN_45 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_45 |
|
R5FSS1_CORE0_INTR_IN_46 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_46 |
|
R5FSS1_CORE0_INTR_IN_47 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_47 |
|
R5FSS1_CORE0_INTR_IN_48 |
CPSW0_CPTS_COMP_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_49 |
RL2_2_ERR_LVL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_50 |
AASRC0_INFIFO_LEVEL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_51 |
AASRC0_INGROUP_LEVEL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_52 |
AASRC0_OUTFIFO_LEVEL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_53 |
AASRC0_OUTGROUP_LEVEL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_54 |
AASRC0_ERR_LEVEL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_55 |
AASRC1_INFIFO_LEVEL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_56 |
AASRC1_INGROUP_LEVEL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_57 |
AASRC1_OUTFIFO_LEVEL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_58 |
AASRC1_OUTGROUP_LEVEL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_59 |
AASRC1_ERR_LEVEL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_60 |
MLB0_MLBSS_MLB_INT_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_61 |
MLB0_MLBSS_MLB_AHB_INT_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_62 |
MLB0_MLBSS_MLB_AHB_INT_OUT_1 |
|
R5FSS1_CORE0_INTR_IN_64 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_65 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_1 |
|
R5FSS1_CORE0_INTR_IN_66 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_2 |
|
R5FSS1_CORE0_INTR_IN_67 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_3 |
|
R5FSS1_CORE0_INTR_IN_68 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_4 |
|
R5FSS1_CORE0_INTR_IN_69 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_5 |
|
R5FSS1_CORE0_INTR_IN_70 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_6 |
|
R5FSS1_CORE0_INTR_IN_71 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_7 |
|
R5FSS1_CORE0_INTR_IN_72 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_8 |
|
R5FSS1_CORE0_INTR_IN_73 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_9 |
|
R5FSS1_CORE0_INTR_IN_74 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_10 |
|
R5FSS1_CORE0_INTR_IN_75 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_11 |
|
R5FSS1_CORE0_INTR_IN_76 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_12 |
|
R5FSS1_CORE0_INTR_IN_77 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_13 |
|
R5FSS1_CORE0_INTR_IN_78 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_14 |
|
R5FSS1_CORE0_INTR_IN_79 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_15 |
|
R5FSS1_CORE0_INTR_IN_80 |
EPWM0_EPWM_TRIPZINT_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_81 |
EPWM1_EPWM_TRIPZINT_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_82 |
EPWM2_EPWM_TRIPZINT_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_83 |
ECAP0_ECAP_INT_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_84 |
ECAP1_ECAP_INT_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_85 |
ECAP2_ECAP_INT_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_86 |
ECAP3_ECAP_INT_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_87 |
ECAP4_ECAP_INT_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_88 |
ECAP5_ECAP_INT_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_90 |
RL2_0_ERR_LVL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_91 |
RL2_2_ERR_LVL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_92 |
RL2_3_ERR_LVL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_93 |
R5FSS1_CORE1_PMU_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_94 |
R5FSS1_CORE0_PMU_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_95 |
R5FSS1_CORE0_VALFIQ_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_96 |
R5FSS1_CORE0_VALIRQ_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_97 |
WKUP_RTCSS0_RTC_EVENT_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_98 |
EFUSE0_EFC_ERROR_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_100 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_24 |
|
R5FSS1_CORE0_INTR_IN_101 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_25 |
|
R5FSS1_CORE0_INTR_IN_102 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_26 |
|
R5FSS1_CORE0_INTR_IN_103 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_27 |
|
R5FSS1_CORE0_INTR_IN_104 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_28 |
|
R5FSS1_CORE0_INTR_IN_105 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_29 |
|
R5FSS1_CORE0_INTR_IN_106 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_30 |
|
R5FSS1_CORE0_INTR_IN_107 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_31 |
|
R5FSS1_CORE0_INTR_IN_108 |
MCU_DCC0_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_109 |
DCC0_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_109 |
DCC1_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_109 |
DCC2_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_109 |
DCC3_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_109 |
DCC4_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_109 |
DCC5_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_109 |
DCC6_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_109 |
DCC7_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_109 |
DCC8_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_113 |
PBIST0_DFT_PBIST_CPU_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_113 |
PBIST5_DFT_PBIST_CPU_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_113 |
PBIST6_DFT_PBIST_CPU_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_113 |
PBIST7_DFT_PBIST_CPU_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_113 |
PBIST8_DFT_PBIST_CPU_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_113 |
PBIST1_DFT_PBIST_CPU_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_113 |
PBIST2_DFT_PBIST_CPU_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_113 |
C7X256V0_CLEC_DFT_PBIST_CPU_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_113 |
C7X256V1_CLEC_DFT_PBIST_CPU_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_113 |
PBIST3_DFT_PBIST_CPU_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_113 |
PBIST4_DFT_PBIST_CPU_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_114 |
WKUP_PBIST0_DFT_PBIST_CPU_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_114 |
WKUP_PBIST1_DFT_PBIST_CPU_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_119 |
MCRC64_0_INT_MCRC_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_120 |
MCASP0_REC_INTR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_121 |
MCASP0_XMIT_INTR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_122 |
MCASP1_REC_INTR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_123 |
MCASP1_XMIT_INTR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_124 |
MCASP2_REC_INTR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_125 |
MCASP2_XMIT_INTR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_126 |
MCASP3_REC_INTR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_127 |
MCASP3_XMIT_INTR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_128 |
MAIN_CTRL_MMR0_ACCESS_ERR_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_128 |
WKUP_CTRL_MMR0_ACCESS_ERR_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_128 |
PADCFG_CTRL0_ACCESS_ERR_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_128 |
MCU_CTRL_MMR0_ACCESS_ERR_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_128 |
MCU_PADCFG_CTRL0_ACCESS_ERR_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_130 |
MCASP4_REC_INTR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_131 |
MCASP4_XMIT_INTR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_134 |
CPSW0_EVNT_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_135 |
CPSW0_MDIO_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_136 |
CPSW0_STAT_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_137 |
MCU_DCC1_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_140 |
WKUP_ESM0_ESM_INT_CFG_LVL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_141 |
WKUP_ESM0_ESM_INT_HI_LVL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_142 |
WKUP_ESM0_ESM_INT_LOW_LVL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_145 |
WKUP_PSC0_PSC_ALLINT_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_146 |
MAIN_PSC0_PSC_ALLINT_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_147 |
CBASS0_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_147 |
CBASS_INFRA1_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_147 |
WKUP_CBASS_SAFE1_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_147 |
CBASS_MCASP0_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_147 |
CBASS_MEM0_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_147 |
CBASS_DBG0_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_147 |
CBASS_CENTRAL2_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_147 |
AM275_MAIN_IPCSS_CBASS0_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_147 |
CBASS_MISC_PERI0_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_147 |
WKUP_CBASS0_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_151 |
ADC0_GEN_LEVEL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_153 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_24 |
|
R5FSS1_CORE0_INTR_IN_154 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_25 |
|
R5FSS1_CORE0_INTR_IN_155 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_26 |
|
R5FSS1_CORE0_INTR_IN_156 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_27 |
|
R5FSS1_CORE0_INTR_IN_157 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_28 |
|
R5FSS1_CORE0_INTR_IN_158 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_29 |
|
R5FSS1_CORE0_INTR_IN_159 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_30 |
|
R5FSS1_CORE0_INTR_IN_160 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_31 |
|
R5FSS1_CORE0_INTR_IN_161 |
MMCSD0_EMMCSDSS_INTR_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_167 |
ESM0_ESM_INT_CFG_LVL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_168 |
ESM0_ESM_INT_HI_LVL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_169 |
ESM0_ESM_INT_LOW_LVL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_171 |
FSS0_OSPI0_LVL_INTR_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_172 |
FSS0_FSAS_FOTA_STAT_INTR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_173 |
FSS0_FSAS_FOTA_STAT_ERR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_174 |
FSS0_OTFA_INTR_ERR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_175 |
R5FSS1_CORE0_CTI_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_176 |
R5FSS1_CORE1_CTI_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_177 |
DDPA0_DDPA_INTR_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_178 |
FSS1_OSPI_0_OSPI_LVL_INTR_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_179 |
FSS1_HYPERBUS1P0_0_HPB_INTR_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_180 |
FSS1_FSAS_0_OTFA_INTR_ERR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_181 |
FSS1_FSAS_0_ECC_INTR_ERR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_182 |
FSS0_FSAS_ECC_INTR_ERR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_183 |
WKUP_VTM0_THERM_LVL_GT_TH1_INTR_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_184 |
WKUP_VTM0_THERM_LVL_GT_TH2_INTR_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_185 |
WKUP_VTM0_THERM_LVL_LT_TH0_INTR_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_186 |
MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_187 |
MCAN2_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_188 |
MCAN3_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_189 |
MCAN4_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_190 |
WKUP_I2C0_POINTRPEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_193 |
I2C0_POINTRPEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_194 |
I2C1_POINTRPEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_195 |
I2C2_POINTRPEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_196 |
I2C3_POINTRPEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_197 |
I2C4_POINTRPEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_198 |
I2C5_POINTRPEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_199 |
I2C6_POINTRPEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_201 |
DEBUGSS0_AQCMPINTR_LEVEL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_202 |
DEBUGSS0_CTM_LEVEL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_203 |
PINFUNCTION_EXTINTNIN_EXTINTN_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_204 |
MCSPI0_INTR_SPI_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_205 |
MCSPI1_INTR_SPI_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_206 |
MCSPI2_INTR_SPI_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_207 |
MCSPI3_INTR_SPI_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_208 |
MCSPI4_INTR_SPI_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_210 |
UART0_USART_IRQ_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_211 |
UART1_USART_IRQ_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_212 |
UART2_USART_IRQ_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_213 |
UART3_USART_IRQ_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_214 |
UART4_USART_IRQ_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_215 |
UART5_USART_IRQ_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_216 |
UART6_USART_IRQ_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_219 |
WKUP_UART0_USART_IRQ_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_220 |
USB0_IRQ_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_221 |
USB0_IRQ_OUT_1 |
|
R5FSS1_CORE0_INTR_IN_222 |
USB0_IRQ_OUT_2 |
|
R5FSS1_CORE0_INTR_IN_223 |
USB0_IRQ_OUT_3 |
|
R5FSS1_CORE0_INTR_IN_224 |
USB0_IRQ_OUT_4 |
|
R5FSS1_CORE0_INTR_IN_225 |
USB0_IRQ_OUT_5 |
|
R5FSS1_CORE0_INTR_IN_226 |
USB0_IRQ_OUT_6 |
|
R5FSS1_CORE0_INTR_IN_227 |
USB0_IRQ_OUT_7 |
|
R5FSS1_CORE0_INTR_IN_228 |
USB0_MISC_LEVEL_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_229 |
MCAN1_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_230 |
MCAN0_MCANSS_MCAN_LVL_INT_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_231 |
MCAN0_MCANSS_MCAN_LVL_INT_OUT_1 |
|
R5FSS1_CORE0_INTR_IN_232 |
MCAN1_MCANSS_MCAN_LVL_INT_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_233 |
MCAN1_MCANSS_MCAN_LVL_INT_OUT_1 |
|
R5FSS1_CORE0_INTR_IN_234 |
MCAN2_MCANSS_MCAN_LVL_INT_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_235 |
MCAN2_MCANSS_MCAN_LVL_INT_OUT_1 |
|
R5FSS1_CORE0_INTR_IN_236 |
MCAN3_MCANSS_MCAN_LVL_INT_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_237 |
MCAN3_MCANSS_MCAN_LVL_INT_OUT_1 |
|
R5FSS1_CORE0_INTR_IN_238 |
MCAN4_MCANSS_MCAN_LVL_INT_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_239 |
MCAN4_MCANSS_MCAN_LVL_INT_OUT_1 |
|
R5FSS1_CORE0_INTR_IN_240 |
MAILBOX0_MAILBOX_CLUSTER_0_MAILBOX_CLUSTER_PEND_OUT_2 |
|
R5FSS1_CORE0_INTR_IN_241 |
MAILBOX0_MAILBOX_CLUSTER_1_MAILBOX_CLUSTER_PEND_OUT_1 |
|
R5FSS1_CORE0_INTR_IN_242 |
MAILBOX0_MAILBOX_CLUSTER_4_MAILBOX_CLUSTER_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_243 |
MAILBOX0_MAILBOX_CLUSTER_6_MAILBOX_CLUSTER_PEND_OUT_2 |
|
R5FSS1_CORE0_INTR_IN_248 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_8 |
|
R5FSS1_CORE0_INTR_IN_249 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_9 |
|
R5FSS1_CORE0_INTR_IN_250 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_10 |
|
R5FSS1_CORE0_INTR_IN_251 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_11 |
|
R5FSS1_CORE0_INTR_IN_252 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_12 |
|
R5FSS1_CORE0_INTR_IN_253 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_13 |
|
R5FSS1_CORE0_INTR_IN_254 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_14 |
|
R5FSS1_CORE0_INTR_IN_255 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_15 |
|
R5FSS1_CORE0_INTR_IN_256 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_8 |
|
R5FSS1_CORE0_INTR_IN_257 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_9 |
|
R5FSS1_CORE0_INTR_IN_258 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_10 |
|
R5FSS1_CORE0_INTR_IN_259 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_11 |
|
R5FSS1_CORE0_INTR_IN_260 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_12 |
|
R5FSS1_CORE0_INTR_IN_261 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_13 |
|
R5FSS1_CORE0_INTR_IN_262 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_14 |
|
R5FSS1_CORE0_INTR_IN_263 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_15 |
|
R5FSS1_CORE0_INTR_IN_264 |
TIMER8_INTR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_265 |
TIMER9_INTR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_266 |
TIMER10_INTR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_267 |
TIMER11_INTR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_268 |
TIMER12_INTR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_269 |
TIMER13_INTR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_270 |
TIMER14_INTR_PEND_OUT_0 |
|
R5FSS1_CORE0_INTR_IN_271 |
TIMER15_INTR_PEND_OUT_0 |
| IN Interrupt | Connected To |
|---|---|
|
R5FSS1_CORE1_INTR_IN_0 |
MAIN_CTRL_MMR0_IPC_SET19_IPC_SET_IPCFG_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_4 |
R5FSS1_CORE1_EXP_INTR_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_5 |
R5FSS1_COMMON0_COMMRX_LEVEL_1_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_6 |
R5FSS1_COMMON0_COMMTX_LEVEL_1_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_7 |
SA3_SS0_INTAGGR_0_INTAGGR_VINTR_OUT_7 |
|
R5FSS1_CORE1_INTR_IN_8 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_16 |
|
R5FSS1_CORE1_INTR_IN_9 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_17 |
|
R5FSS1_CORE1_INTR_IN_10 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_18 |
|
R5FSS1_CORE1_INTR_IN_11 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_19 |
|
R5FSS1_CORE1_INTR_IN_12 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_20 |
|
R5FSS1_CORE1_INTR_IN_13 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_21 |
|
R5FSS1_CORE1_INTR_IN_14 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_22 |
|
R5FSS1_CORE1_INTR_IN_15 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_23 |
|
R5FSS1_CORE1_INTR_IN_16 |
SA3_SS0_SA_UL_0_SA_UL_PKA_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_17 |
SA3_SS0_SA_UL_0_SA_UL_TRNG_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_22 |
TIMER6_INTR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_23 |
TIMER7_INTR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_24 |
TIMER0_INTR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_25 |
TIMER1_INTR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_26 |
TIMER2_INTR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_27 |
TIMER3_INTR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_28 |
TIMER4_INTR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_29 |
TIMER5_INTR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_30 |
RTI3_INTR_WWD_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_31 |
WKUP_CBASS_SAFE1_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_32 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_32 |
|
R5FSS1_CORE1_INTR_IN_33 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_33 |
|
R5FSS1_CORE1_INTR_IN_34 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_34 |
|
R5FSS1_CORE1_INTR_IN_35 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_35 |
|
R5FSS1_CORE1_INTR_IN_36 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_36 |
|
R5FSS1_CORE1_INTR_IN_37 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_37 |
|
R5FSS1_CORE1_INTR_IN_38 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_38 |
|
R5FSS1_CORE1_INTR_IN_39 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_39 |
|
R5FSS1_CORE1_INTR_IN_40 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_40 |
|
R5FSS1_CORE1_INTR_IN_41 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_41 |
|
R5FSS1_CORE1_INTR_IN_42 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_42 |
|
R5FSS1_CORE1_INTR_IN_43 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_43 |
|
R5FSS1_CORE1_INTR_IN_44 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_44 |
|
R5FSS1_CORE1_INTR_IN_45 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_45 |
|
R5FSS1_CORE1_INTR_IN_46 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_46 |
|
R5FSS1_CORE1_INTR_IN_47 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_47 |
|
R5FSS1_CORE1_INTR_IN_48 |
CPSW0_CPTS_COMP_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_49 |
RL2_3_ERR_LVL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_50 |
AASRC0_INFIFO_LEVEL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_51 |
AASRC0_INGROUP_LEVEL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_52 |
AASRC0_OUTFIFO_LEVEL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_53 |
AASRC0_OUTGROUP_LEVEL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_54 |
AASRC0_ERR_LEVEL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_55 |
AASRC1_INFIFO_LEVEL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_56 |
AASRC1_INGROUP_LEVEL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_57 |
AASRC1_OUTFIFO_LEVEL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_58 |
AASRC1_OUTGROUP_LEVEL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_59 |
AASRC1_ERR_LEVEL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_60 |
MLB0_MLBSS_MLB_INT_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_61 |
MLB0_MLBSS_MLB_AHB_INT_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_62 |
MLB0_MLBSS_MLB_AHB_INT_OUT_1 |
|
R5FSS1_CORE1_INTR_IN_64 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_65 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_1 |
|
R5FSS1_CORE1_INTR_IN_66 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_2 |
|
R5FSS1_CORE1_INTR_IN_67 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_3 |
|
R5FSS1_CORE1_INTR_IN_68 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_4 |
|
R5FSS1_CORE1_INTR_IN_69 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_5 |
|
R5FSS1_CORE1_INTR_IN_70 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_6 |
|
R5FSS1_CORE1_INTR_IN_71 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_7 |
|
R5FSS1_CORE1_INTR_IN_72 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_8 |
|
R5FSS1_CORE1_INTR_IN_73 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_9 |
|
R5FSS1_CORE1_INTR_IN_74 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_10 |
|
R5FSS1_CORE1_INTR_IN_75 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_11 |
|
R5FSS1_CORE1_INTR_IN_76 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_12 |
|
R5FSS1_CORE1_INTR_IN_77 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_13 |
|
R5FSS1_CORE1_INTR_IN_78 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_14 |
|
R5FSS1_CORE1_INTR_IN_79 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_15 |
|
R5FSS1_CORE1_INTR_IN_80 |
EPWM0_EPWM_TRIPZINT_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_81 |
EPWM1_EPWM_TRIPZINT_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_82 |
EPWM2_EPWM_TRIPZINT_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_83 |
ECAP0_ECAP_INT_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_84 |
ECAP1_ECAP_INT_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_85 |
ECAP2_ECAP_INT_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_86 |
ECAP3_ECAP_INT_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_87 |
ECAP4_ECAP_INT_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_88 |
ECAP5_ECAP_INT_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_90 |
RL2_0_ERR_LVL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_91 |
RL2_2_ERR_LVL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_92 |
RL2_3_ERR_LVL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_93 |
R5FSS1_CORE1_PMU_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_94 |
R5FSS1_CORE0_PMU_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_95 |
R5FSS1_CORE1_VALFIQ_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_96 |
R5FSS1_CORE1_VALIRQ_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_97 |
WKUP_RTCSS0_RTC_EVENT_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_98 |
EFUSE0_EFC_ERROR_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_100 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_24 |
|
R5FSS1_CORE1_INTR_IN_101 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_25 |
|
R5FSS1_CORE1_INTR_IN_102 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_26 |
|
R5FSS1_CORE1_INTR_IN_103 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_27 |
|
R5FSS1_CORE1_INTR_IN_104 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_28 |
|
R5FSS1_CORE1_INTR_IN_105 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_29 |
|
R5FSS1_CORE1_INTR_IN_106 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_30 |
|
R5FSS1_CORE1_INTR_IN_107 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_31 |
|
R5FSS1_CORE1_INTR_IN_108 |
MCU_DCC0_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_109 |
DCC0_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_109 |
DCC1_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_109 |
DCC2_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_109 |
DCC3_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_109 |
DCC4_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_109 |
DCC5_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_109 |
DCC6_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_109 |
DCC7_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_109 |
DCC8_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_113 |
PBIST0_DFT_PBIST_CPU_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_113 |
PBIST5_DFT_PBIST_CPU_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_113 |
PBIST6_DFT_PBIST_CPU_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_113 |
PBIST7_DFT_PBIST_CPU_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_113 |
PBIST8_DFT_PBIST_CPU_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_113 |
PBIST1_DFT_PBIST_CPU_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_113 |
PBIST2_DFT_PBIST_CPU_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_113 |
C7X256V0_CLEC_DFT_PBIST_CPU_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_113 |
C7X256V1_CLEC_DFT_PBIST_CPU_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_113 |
PBIST3_DFT_PBIST_CPU_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_113 |
PBIST4_DFT_PBIST_CPU_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_114 |
WKUP_PBIST0_DFT_PBIST_CPU_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_114 |
WKUP_PBIST1_DFT_PBIST_CPU_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_119 |
MCRC64_0_INT_MCRC_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_120 |
MCASP0_REC_INTR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_121 |
MCASP0_XMIT_INTR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_122 |
MCASP1_REC_INTR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_123 |
MCASP1_XMIT_INTR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_124 |
MCASP2_REC_INTR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_125 |
MCASP2_XMIT_INTR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_126 |
MCASP3_REC_INTR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_127 |
MCASP3_XMIT_INTR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_128 |
MAIN_CTRL_MMR0_ACCESS_ERR_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_128 |
WKUP_CTRL_MMR0_ACCESS_ERR_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_128 |
PADCFG_CTRL0_ACCESS_ERR_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_128 |
MCU_CTRL_MMR0_ACCESS_ERR_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_128 |
MCU_PADCFG_CTRL0_ACCESS_ERR_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_130 |
MCASP4_REC_INTR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_131 |
MCASP4_XMIT_INTR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_134 |
CPSW0_EVNT_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_135 |
CPSW0_MDIO_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_136 |
CPSW0_STAT_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_137 |
MCU_DCC1_INTR_DONE_LEVEL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_140 |
WKUP_ESM0_ESM_INT_CFG_LVL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_141 |
WKUP_ESM0_ESM_INT_HI_LVL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_142 |
WKUP_ESM0_ESM_INT_LOW_LVL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_145 |
WKUP_PSC0_PSC_ALLINT_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_146 |
MAIN_PSC0_PSC_ALLINT_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_147 |
CBASS0_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_147 |
CBASS_INFRA1_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_147 |
WKUP_CBASS_SAFE1_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_147 |
CBASS_MCASP0_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_147 |
CBASS_MEM0_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_147 |
CBASS_DBG0_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_147 |
CBASS_CENTRAL2_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_147 |
AM275_MAIN_IPCSS_CBASS0_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_147 |
CBASS_MISC_PERI0_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_147 |
WKUP_CBASS0_DEFAULT_ERR_INTR_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_151 |
ADC0_GEN_LEVEL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_153 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_24 |
|
R5FSS1_CORE1_INTR_IN_154 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_25 |
|
R5FSS1_CORE1_INTR_IN_155 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_26 |
|
R5FSS1_CORE1_INTR_IN_156 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_27 |
|
R5FSS1_CORE1_INTR_IN_157 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_28 |
|
R5FSS1_CORE1_INTR_IN_158 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_29 |
|
R5FSS1_CORE1_INTR_IN_159 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_30 |
|
R5FSS1_CORE1_INTR_IN_160 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_31 |
|
R5FSS1_CORE1_INTR_IN_161 |
MMCSD0_EMMCSDSS_INTR_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_167 |
ESM0_ESM_INT_CFG_LVL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_168 |
ESM0_ESM_INT_HI_LVL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_169 |
ESM0_ESM_INT_LOW_LVL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_171 |
FSS0_OSPI0_LVL_INTR_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_172 |
FSS0_FSAS_FOTA_STAT_INTR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_173 |
FSS0_FSAS_FOTA_STAT_ERR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_174 |
FSS0_OTFA_INTR_ERR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_175 |
R5FSS1_CORE0_CTI_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_176 |
R5FSS1_CORE1_CTI_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_177 |
DDPA0_DDPA_INTR_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_178 |
FSS1_OSPI_0_OSPI_LVL_INTR_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_179 |
FSS1_HYPERBUS1P0_0_HPB_INTR_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_180 |
FSS1_FSAS_0_OTFA_INTR_ERR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_181 |
FSS1_FSAS_0_ECC_INTR_ERR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_182 |
FSS0_FSAS_ECC_INTR_ERR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_183 |
WKUP_VTM0_THERM_LVL_GT_TH1_INTR_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_184 |
WKUP_VTM0_THERM_LVL_GT_TH2_INTR_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_185 |
WKUP_VTM0_THERM_LVL_LT_TH0_INTR_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_186 |
MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_187 |
MCAN2_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_188 |
MCAN3_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_189 |
MCAN4_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_190 |
WKUP_I2C0_POINTRPEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_193 |
I2C0_POINTRPEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_194 |
I2C1_POINTRPEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_195 |
I2C2_POINTRPEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_196 |
I2C3_POINTRPEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_197 |
I2C4_POINTRPEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_198 |
I2C5_POINTRPEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_199 |
I2C6_POINTRPEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_201 |
DEBUGSS0_AQCMPINTR_LEVEL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_202 |
DEBUGSS0_CTM_LEVEL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_203 |
PINFUNCTION_EXTINTNIN_EXTINTN_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_204 |
MCSPI0_INTR_SPI_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_205 |
MCSPI1_INTR_SPI_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_206 |
MCSPI2_INTR_SPI_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_207 |
MCSPI3_INTR_SPI_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_208 |
MCSPI4_INTR_SPI_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_210 |
UART0_USART_IRQ_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_211 |
UART1_USART_IRQ_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_212 |
UART2_USART_IRQ_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_213 |
UART3_USART_IRQ_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_214 |
UART4_USART_IRQ_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_215 |
UART5_USART_IRQ_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_216 |
UART6_USART_IRQ_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_219 |
WKUP_UART0_USART_IRQ_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_220 |
USB0_IRQ_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_221 |
USB0_IRQ_OUT_1 |
|
R5FSS1_CORE1_INTR_IN_222 |
USB0_IRQ_OUT_2 |
|
R5FSS1_CORE1_INTR_IN_223 |
USB0_IRQ_OUT_3 |
|
R5FSS1_CORE1_INTR_IN_224 |
USB0_IRQ_OUT_4 |
|
R5FSS1_CORE1_INTR_IN_225 |
USB0_IRQ_OUT_5 |
|
R5FSS1_CORE1_INTR_IN_226 |
USB0_IRQ_OUT_6 |
|
R5FSS1_CORE1_INTR_IN_227 |
USB0_IRQ_OUT_7 |
|
R5FSS1_CORE1_INTR_IN_228 |
USB0_MISC_LEVEL_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_229 |
MCAN1_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_230 |
MCAN0_MCANSS_MCAN_LVL_INT_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_231 |
MCAN0_MCANSS_MCAN_LVL_INT_OUT_1 |
|
R5FSS1_CORE1_INTR_IN_232 |
MCAN1_MCANSS_MCAN_LVL_INT_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_233 |
MCAN1_MCANSS_MCAN_LVL_INT_OUT_1 |
|
R5FSS1_CORE1_INTR_IN_234 |
MCAN2_MCANSS_MCAN_LVL_INT_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_235 |
MCAN2_MCANSS_MCAN_LVL_INT_OUT_1 |
|
R5FSS1_CORE1_INTR_IN_236 |
MCAN3_MCANSS_MCAN_LVL_INT_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_237 |
MCAN3_MCANSS_MCAN_LVL_INT_OUT_1 |
|
R5FSS1_CORE1_INTR_IN_238 |
MCAN4_MCANSS_MCAN_LVL_INT_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_239 |
MCAN4_MCANSS_MCAN_LVL_INT_OUT_1 |
|
R5FSS1_CORE1_INTR_IN_240 |
MAILBOX0_MAILBOX_CLUSTER_0_MAILBOX_CLUSTER_PEND_OUT_3 |
|
R5FSS1_CORE1_INTR_IN_241 |
MAILBOX0_MAILBOX_CLUSTER_2_MAILBOX_CLUSTER_PEND_OUT_1 |
|
R5FSS1_CORE1_INTR_IN_242 |
MAILBOX0_MAILBOX_CLUSTER_4_MAILBOX_CLUSTER_PEND_OUT_1 |
|
R5FSS1_CORE1_INTR_IN_243 |
MAILBOX0_MAILBOX_CLUSTER_5_MAILBOX_CLUSTER_PEND_OUT_2 |
|
R5FSS1_CORE1_INTR_IN_248 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_8 |
|
R5FSS1_CORE1_INTR_IN_249 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_9 |
|
R5FSS1_CORE1_INTR_IN_250 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_10 |
|
R5FSS1_CORE1_INTR_IN_251 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_11 |
|
R5FSS1_CORE1_INTR_IN_252 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_12 |
|
R5FSS1_CORE1_INTR_IN_253 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_13 |
|
R5FSS1_CORE1_INTR_IN_254 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_14 |
|
R5FSS1_CORE1_INTR_IN_255 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_15 |
|
R5FSS1_CORE1_INTR_IN_256 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_8 |
|
R5FSS1_CORE1_INTR_IN_257 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_9 |
|
R5FSS1_CORE1_INTR_IN_258 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_10 |
|
R5FSS1_CORE1_INTR_IN_259 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_11 |
|
R5FSS1_CORE1_INTR_IN_260 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_12 |
|
R5FSS1_CORE1_INTR_IN_261 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_13 |
|
R5FSS1_CORE1_INTR_IN_262 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_14 |
|
R5FSS1_CORE1_INTR_IN_263 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_15 |
|
R5FSS1_CORE1_INTR_IN_264 |
TIMER8_INTR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_265 |
TIMER9_INTR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_266 |
TIMER10_INTR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_267 |
TIMER11_INTR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_268 |
TIMER12_INTR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_269 |
TIMER13_INTR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_270 |
TIMER14_INTR_PEND_OUT_0 |
|
R5FSS1_CORE1_INTR_IN_271 |
TIMER15_INTR_PEND_OUT_0 |
| IN Interrupt | Connected To |
|---|---|
|
WKUP_R5FSS0_CORE0_INTR_IN_0 |
MCU_CTRL_MMR0_IPC_SET0_IPC_SET_IPCFG_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_4 |
WKUP_R5FSS0_CORE0_EXP_INTR_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_5 |
WKUP_R5FSS0_COMMON0_COMMRX_LEVEL_0_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_6 |
WKUP_R5FSS0_COMMON0_COMMTX_LEVEL_0_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_7 |
SA3_SS0_INTAGGR_0_INTAGGR_VINTR_OUT_6 |
|
WKUP_R5FSS0_CORE0_INTR_IN_8 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_72 |
|
WKUP_R5FSS0_CORE0_INTR_IN_9 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_73 |
|
WKUP_R5FSS0_CORE0_INTR_IN_10 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_74 |
|
WKUP_R5FSS0_CORE0_INTR_IN_11 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_75 |
|
WKUP_R5FSS0_CORE0_INTR_IN_12 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_76 |
|
WKUP_R5FSS0_CORE0_INTR_IN_13 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_77 |
|
WKUP_R5FSS0_CORE0_INTR_IN_14 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_78 |
|
WKUP_R5FSS0_CORE0_INTR_IN_15 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_79 |
|
WKUP_R5FSS0_CORE0_INTR_IN_16 |
SA3_SS0_SA_UL_0_SA_UL_PKA_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_17 |
SA3_SS0_SA_UL_0_SA_UL_TRNG_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_18 |
MCU_GPIO0_GPIO_LVL_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_23 |
WKUP_ICEMELTER0_PSC_FORCE_POWER_ON_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_28 |
WKUP_TIMER0_TIMER_CLKSTOP_WAKEUP_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_29 |
WKUP_TIMER1_TIMER_CLKSTOP_WAKEUP_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_30 |
WKUP_RTI0_INTR_WWD_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_32 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_33 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_1 |
|
WKUP_R5FSS0_CORE0_INTR_IN_34 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_2 |
|
WKUP_R5FSS0_CORE0_INTR_IN_35 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_3 |
|
WKUP_R5FSS0_CORE0_INTR_IN_36 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_4 |
|
WKUP_R5FSS0_CORE0_INTR_IN_37 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_5 |
|
WKUP_R5FSS0_CORE0_INTR_IN_38 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_6 |
|
WKUP_R5FSS0_CORE0_INTR_IN_39 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_7 |
|
WKUP_R5FSS0_CORE0_INTR_IN_40 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_8 |
|
WKUP_R5FSS0_CORE0_INTR_IN_41 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_9 |
|
WKUP_R5FSS0_CORE0_INTR_IN_42 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_10 |
|
WKUP_R5FSS0_CORE0_INTR_IN_43 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_11 |
|
WKUP_R5FSS0_CORE0_INTR_IN_44 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_12 |
|
WKUP_R5FSS0_CORE0_INTR_IN_45 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_13 |
|
WKUP_R5FSS0_CORE0_INTR_IN_46 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_14 |
|
WKUP_R5FSS0_CORE0_INTR_IN_47 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_15 |
|
WKUP_R5FSS0_CORE0_INTR_IN_48 |
CPSW0_CPTS_COMP_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_50 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_12 |
|
WKUP_R5FSS0_CORE0_INTR_IN_51 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_13 |
|
WKUP_R5FSS0_CORE0_INTR_IN_52 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_14 |
|
WKUP_R5FSS0_CORE0_INTR_IN_53 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_15 |
|
WKUP_R5FSS0_CORE0_INTR_IN_56 |
GPIO0_GPIO_BANK_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_57 |
GPIO0_GPIO_BANK_OUT_1 |
|
WKUP_R5FSS0_CORE0_INTR_IN_58 |
WKUP_R5FSS0_CORE0_PMU_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_59 |
WKUP_R5FSS0_CORE0_VALFIQ_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_60 |
WKUP_R5FSS0_CORE0_VALIRQ_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_61 |
USB0_USB_WAKEUP_CLKSTOP_WAKEUP_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_64 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_40 |
|
WKUP_R5FSS0_CORE0_INTR_IN_65 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_41 |
|
WKUP_R5FSS0_CORE0_INTR_IN_66 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_42 |
|
WKUP_R5FSS0_CORE0_INTR_IN_67 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_43 |
|
WKUP_R5FSS0_CORE0_INTR_IN_68 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_44 |
|
WKUP_R5FSS0_CORE0_INTR_IN_69 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_45 |
|
WKUP_R5FSS0_CORE0_INTR_IN_70 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_46 |
|
WKUP_R5FSS0_CORE0_INTR_IN_71 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_47 |
|
WKUP_R5FSS0_CORE0_INTR_IN_72 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_48 |
|
WKUP_R5FSS0_CORE0_INTR_IN_73 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_49 |
|
WKUP_R5FSS0_CORE0_INTR_IN_74 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_50 |
|
WKUP_R5FSS0_CORE0_INTR_IN_75 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_51 |
|
WKUP_R5FSS0_CORE0_INTR_IN_76 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_52 |
|
WKUP_R5FSS0_CORE0_INTR_IN_77 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_53 |
|
WKUP_R5FSS0_CORE0_INTR_IN_78 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_54 |
|
WKUP_R5FSS0_CORE0_INTR_IN_79 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_55 |
|
WKUP_R5FSS0_CORE0_INTR_IN_80 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_56 |
|
WKUP_R5FSS0_CORE0_INTR_IN_81 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_57 |
|
WKUP_R5FSS0_CORE0_INTR_IN_82 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_58 |
|
WKUP_R5FSS0_CORE0_INTR_IN_83 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_59 |
|
WKUP_R5FSS0_CORE0_INTR_IN_84 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_60 |
|
WKUP_R5FSS0_CORE0_INTR_IN_85 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_61 |
|
WKUP_R5FSS0_CORE0_INTR_IN_86 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_62 |
|
WKUP_R5FSS0_CORE0_INTR_IN_87 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_63 |
|
WKUP_R5FSS0_CORE0_INTR_IN_88 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_64 |
|
WKUP_R5FSS0_CORE0_INTR_IN_89 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_65 |
|
WKUP_R5FSS0_CORE0_INTR_IN_90 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_66 |
|
WKUP_R5FSS0_CORE0_INTR_IN_91 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_67 |
|
WKUP_R5FSS0_CORE0_INTR_IN_92 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_68 |
|
WKUP_R5FSS0_CORE0_INTR_IN_93 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_69 |
|
WKUP_R5FSS0_CORE0_INTR_IN_94 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_70 |
|
WKUP_R5FSS0_CORE0_INTR_IN_95 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_71 |
|
WKUP_R5FSS0_CORE0_INTR_IN_97 |
WKUP_RTCSS0_RTC_EVENT_PEND_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_98 |
EFUSE0_EFC_ERROR_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_104 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_105 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_1 |
|
WKUP_R5FSS0_CORE0_INTR_IN_106 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_2 |
|
WKUP_R5FSS0_CORE0_INTR_IN_107 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_3 |
|
WKUP_R5FSS0_CORE0_INTR_IN_108 |
MCU_DCC0_INTR_DONE_LEVEL_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_109 |
DCC0_INTR_DONE_LEVEL_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_109 |
DCC1_INTR_DONE_LEVEL_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_109 |
DCC2_INTR_DONE_LEVEL_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_109 |
DCC3_INTR_DONE_LEVEL_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_109 |
DCC4_INTR_DONE_LEVEL_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_109 |
DCC5_INTR_DONE_LEVEL_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_109 |
DCC6_INTR_DONE_LEVEL_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_109 |
DCC7_INTR_DONE_LEVEL_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_109 |
DCC8_INTR_DONE_LEVEL_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_113 |
PBIST0_DFT_PBIST_CPU_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_113 |
PBIST5_DFT_PBIST_CPU_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_113 |
PBIST6_DFT_PBIST_CPU_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_113 |
PBIST7_DFT_PBIST_CPU_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_113 |
PBIST8_DFT_PBIST_CPU_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_113 |
PBIST1_DFT_PBIST_CPU_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_113 |
PBIST2_DFT_PBIST_CPU_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_113 |
C7X256V0_CLEC_DFT_PBIST_CPU_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_113 |
C7X256V1_CLEC_DFT_PBIST_CPU_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_113 |
PBIST3_DFT_PBIST_CPU_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_113 |
PBIST4_DFT_PBIST_CPU_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_114 |
WKUP_PBIST0_DFT_PBIST_CPU_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_114 |
WKUP_PBIST1_DFT_PBIST_CPU_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_119 |
MCRC64_0_INT_MCRC_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_120 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_24 |
|
WKUP_R5FSS0_CORE0_INTR_IN_121 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_25 |
|
WKUP_R5FSS0_CORE0_INTR_IN_122 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_26 |
|
WKUP_R5FSS0_CORE0_INTR_IN_123 |
EPWM0_EPWM_ETINT_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_124 |
EPWM0_EPWM_TRIPZINT_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_125 |
EPWM1_EPWM_ETINT_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_126 |
EPWM1_EPWM_TRIPZINT_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_127 |
EPWM2_EPWM_ETINT_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_128 |
MAIN_CTRL_MMR0_ACCESS_ERR_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_128 |
WKUP_CTRL_MMR0_ACCESS_ERR_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_128 |
PADCFG_CTRL0_ACCESS_ERR_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_128 |
MCU_CTRL_MMR0_ACCESS_ERR_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_128 |
MCU_PADCFG_CTRL0_ACCESS_ERR_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_134 |
CPSW0_EVNT_PEND_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_135 |
CPSW0_MDIO_PEND_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_136 |
CPSW0_STAT_PEND_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_137 |
MCU_DCC1_INTR_DONE_LEVEL_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_138 |
WKUP_TIMER0_INTR_PEND_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_139 |
WKUP_TIMER1_INTR_PEND_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_140 |
WKUP_ESM0_ESM_INT_CFG_LVL_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_141 |
WKUP_ESM0_ESM_INT_HI_LVL_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_142 |
WKUP_ESM0_ESM_INT_LOW_LVL_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_143 |
WKUP_I2C0_CLKSTOP_WAKEUP_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_144 |
WKUP_UART0_CLKSTOP_WAKEUP_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_145 |
WKUP_PSC0_PSC_ALLINT_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_146 |
MAIN_PSC0_PSC_ALLINT_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_147 |
CBASS0_DEFAULT_ERR_INTR_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_147 |
CBASS_INFRA1_DEFAULT_ERR_INTR_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_147 |
WKUP_CBASS_SAFE1_DEFAULT_ERR_INTR_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_147 |
CBASS_MCASP0_DEFAULT_ERR_INTR_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_147 |
CBASS_MEM0_DEFAULT_ERR_INTR_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_147 |
CBASS_DBG0_DEFAULT_ERR_INTR_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_147 |
CBASS_CENTRAL2_DEFAULT_ERR_INTR_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_147 |
AM275_MAIN_IPCSS_CBASS0_DEFAULT_ERR_INTR_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_147 |
CBASS_MISC_PERI0_DEFAULT_ERR_INTR_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_147 |
WKUP_CBASS0_DEFAULT_ERR_INTR_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_148 |
EPWM2_EPWM_TRIPZINT_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_151 |
ADC0_GEN_LEVEL_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_161 |
MMCSD0_EMMCSDSS_INTR_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_165 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_27 |
|
WKUP_R5FSS0_CORE0_INTR_IN_167 |
ESM0_ESM_INT_CFG_LVL_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_168 |
ESM0_ESM_INT_HI_LVL_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_169 |
ESM0_ESM_INT_LOW_LVL_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_171 |
FSS0_OSPI0_LVL_INTR_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_172 |
FSS0_FSAS_FOTA_STAT_INTR_PEND_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_173 |
FSS0_FSAS_FOTA_STAT_ERR_PEND_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_174 |
FSS0_OTFA_INTR_ERR_PEND_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_175 |
WKUP_R5FSS0_CORE0_CTI_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_177 |
DDPA0_DDPA_INTR_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_178 |
FSS1_OSPI_0_OSPI_LVL_INTR_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_179 |
FSS1_HYPERBUS1P0_0_HPB_INTR_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_180 |
FSS1_FSAS_0_OTFA_INTR_ERR_PEND_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_181 |
FSS1_FSAS_0_ECC_INTR_ERR_PEND_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_182 |
FSS0_FSAS_ECC_INTR_ERR_PEND_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_183 |
WKUP_VTM0_THERM_LVL_GT_TH1_INTR_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_184 |
WKUP_VTM0_THERM_LVL_GT_TH2_INTR_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_185 |
WKUP_VTM0_THERM_LVL_LT_TH0_INTR_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_186 |
MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_187 |
MCAN2_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_188 |
MCAN3_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_189 |
MCAN4_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_190 |
WKUP_I2C0_POINTRPEND_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_193 |
I2C0_POINTRPEND_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_194 |
I2C1_POINTRPEND_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_195 |
I2C2_POINTRPEND_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_196 |
I2C3_POINTRPEND_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_197 |
I2C4_POINTRPEND_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_198 |
I2C5_POINTRPEND_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_199 |
I2C6_POINTRPEND_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_201 |
DEBUGSS0_AQCMPINTR_LEVEL_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_202 |
DEBUGSS0_CTM_LEVEL_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_203 |
PINFUNCTION_EXTINTNIN_EXTINTN_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_204 |
MCSPI0_INTR_SPI_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_205 |
MCSPI1_INTR_SPI_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_206 |
MCSPI2_INTR_SPI_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_207 |
MCSPI3_INTR_SPI_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_208 |
MCSPI4_INTR_SPI_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_210 |
UART0_USART_IRQ_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_211 |
UART1_USART_IRQ_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_212 |
UART2_USART_IRQ_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_213 |
UART3_USART_IRQ_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_214 |
UART4_USART_IRQ_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_215 |
UART5_USART_IRQ_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_216 |
UART6_USART_IRQ_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_219 |
WKUP_UART0_USART_IRQ_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_220 |
USB0_IRQ_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_221 |
USB0_IRQ_OUT_1 |
|
WKUP_R5FSS0_CORE0_INTR_IN_222 |
USB0_IRQ_OUT_2 |
|
WKUP_R5FSS0_CORE0_INTR_IN_223 |
USB0_IRQ_OUT_3 |
|
WKUP_R5FSS0_CORE0_INTR_IN_224 |
USB0_IRQ_OUT_4 |
|
WKUP_R5FSS0_CORE0_INTR_IN_225 |
USB0_IRQ_OUT_5 |
|
WKUP_R5FSS0_CORE0_INTR_IN_226 |
USB0_IRQ_OUT_6 |
|
WKUP_R5FSS0_CORE0_INTR_IN_227 |
USB0_IRQ_OUT_7 |
|
WKUP_R5FSS0_CORE0_INTR_IN_228 |
USB0_MISC_LEVEL_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_229 |
MCAN1_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_230 |
MCAN0_MCANSS_MCAN_LVL_INT_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_231 |
MCAN0_MCANSS_MCAN_LVL_INT_OUT_1 |
|
WKUP_R5FSS0_CORE0_INTR_IN_232 |
MCAN1_MCANSS_MCAN_LVL_INT_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_233 |
MCAN1_MCANSS_MCAN_LVL_INT_OUT_1 |
|
WKUP_R5FSS0_CORE0_INTR_IN_234 |
MCAN2_MCANSS_MCAN_LVL_INT_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_235 |
MCAN2_MCANSS_MCAN_LVL_INT_OUT_1 |
|
WKUP_R5FSS0_CORE0_INTR_IN_236 |
MCAN3_MCANSS_MCAN_LVL_INT_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_237 |
MCAN3_MCANSS_MCAN_LVL_INT_OUT_1 |
|
WKUP_R5FSS0_CORE0_INTR_IN_238 |
MCAN4_MCANSS_MCAN_LVL_INT_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_239 |
MCAN4_MCANSS_MCAN_LVL_INT_OUT_1 |
|
WKUP_R5FSS0_CORE0_INTR_IN_240 |
MAILBOX0_MAILBOX_CLUSTER_5_MAILBOX_CLUSTER_PEND_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_241 |
MAILBOX0_MAILBOX_CLUSTER_6_MAILBOX_CLUSTER_PEND_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_242 |
MAILBOX0_MAILBOX_CLUSTER_7_MAILBOX_CLUSTER_PEND_OUT_0 |
|
WKUP_R5FSS0_CORE0_INTR_IN_249 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_24 |
|
WKUP_R5FSS0_CORE0_INTR_IN_250 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_25 |
|
WKUP_R5FSS0_CORE0_INTR_IN_254 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_26 |
|
WKUP_R5FSS0_CORE0_INTR_IN_255 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_27 |
| Instance | OUT Interrupt | Connected To |
|---|---|---|
|
R5FSS0 |
R5FSS0_CCM_COMPARE_STAT_PULSE_INTR_OUT_0 |
ESM0_ESM_PLS_EVENT0_IN_230 |
|
R5FSS0_CCM_COMPARE_STAT_PULSE_INTR_OUT_0 |
ESM0_ESM_PLS_EVENT1_IN_230 |
|
|
R5FSS0_CCM_COMPARE_STAT_PULSE_INTR_OUT_0 |
ESM0_ESM_PLS_EVENT2_IN_230 |
|
|
R5FSS0_CORE0 |
R5FSS0_CORE0_CTI_OUT_0 |
R5FSS0_CORE0_INTR_IN_175 |
|
R5FSS0_CORE0_CTI_OUT_0 |
R5FSS0_CORE1_INTR_IN_175 |
|
|
R5FSS0_CORE0_EXP_INTR_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_210 |
|
|
R5FSS0_CORE0_EXP_INTR_OUT_0 |
R5FSS0_CORE0_INTR_IN_4 |
|
|
R5FSS0_CORE0_PMU_OUT_0 |
R5FSS0_CORE0_INTR_IN_94 |
|
|
R5FSS0_CORE0_PMU_OUT_0 |
R5FSS0_CORE1_INTR_IN_94 |
|
|
R5FSS0_CORE0_VALFIQ_OUT_0 |
R5FSS0_CORE0_INTR_IN_95 |
|
|
R5FSS0_CORE0_VALIRQ_OUT_0 |
R5FSS0_CORE0_INTR_IN_96 |
|
|
R5FSS0_CORE1 |
R5FSS0_CORE1_CTI_OUT_0 |
R5FSS0_CORE0_INTR_IN_176 |
|
R5FSS0_CORE1_CTI_OUT_0 |
R5FSS0_CORE1_INTR_IN_176 |
|
|
R5FSS0_CORE1_EXP_INTR_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_6 |
|
|
R5FSS0_CORE1_EXP_INTR_OUT_0 |
R5FSS0_CORE1_INTR_IN_4 |
|
|
R5FSS0_CORE1_PMU_OUT_0 |
R5FSS0_CORE0_INTR_IN_93 |
|
|
R5FSS0_CORE1_PMU_OUT_0 |
R5FSS0_CORE1_INTR_IN_93 |
|
|
R5FSS0_CORE1_VALFIQ_OUT_0 |
R5FSS0_CORE1_INTR_IN_95 |
|
|
R5FSS0_CORE1_VALIRQ_OUT_0 |
R5FSS0_CORE1_INTR_IN_96 |
|
|
R5FSS0_CORE0_ECC_AGGR |
R5FSS0_CORE0_ECC_AGGR_ECC_CORRECTED_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_208 |
|
R5FSS0_CORE0_ECC_AGGR_ECC_UNCORRECTED_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_209 |
|
|
R5FSS0_CORE1_ECC_AGGR |
R5FSS0_CORE1_ECC_AGGR_ECC_CORRECTED_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_219 |
|
R5FSS0_CORE1_ECC_AGGR_ECC_UNCORRECTED_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_220 |
|
|
R5FSS0_COMMON0 |
R5FSS0_COMMON0_BUS_MONITOR_ERR_PULSE_OUT_0 |
ESM0_ESM_PLS_EVENT0_IN_229 |
|
R5FSS0_COMMON0_BUS_MONITOR_ERR_PULSE_OUT_0 |
ESM0_ESM_PLS_EVENT1_IN_229 |
|
|
R5FSS0_COMMON0_BUS_MONITOR_ERR_PULSE_OUT_0 |
ESM0_ESM_PLS_EVENT2_IN_229 |
|
|
R5FSS0_COMMON0_COMMRX_LEVEL_0_OUT_0 |
R5FSS0_CORE0_INTR_IN_5 |
|
|
R5FSS0_COMMON0_COMMRX_LEVEL_1_OUT_0 |
R5FSS0_CORE1_INTR_IN_5 |
|
|
R5FSS0_COMMON0_COMMTX_LEVEL_0_OUT_0 |
R5FSS0_CORE0_INTR_IN_6 |
|
|
R5FSS0_COMMON0_COMMTX_LEVEL_1_OUT_0 |
R5FSS0_CORE1_INTR_IN_6 |
|
|
R5FSS0_COMMON0_COMPARE_ERR_PULSE_OUT_0 |
ESM0_ESM_PLS_EVENT0_IN_231 |
|
|
R5FSS0_COMMON0_COMPARE_ERR_PULSE_OUT_0 |
ESM0_ESM_PLS_EVENT1_IN_231 |
|
|
R5FSS0_COMMON0_COMPARE_ERR_PULSE_OUT_0 |
ESM0_ESM_PLS_EVENT2_IN_231 |
|
|
R5FSS0_COMMON0_ECC_DE_TO_ESM_0_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_211 |
|
|
R5FSS0_COMMON0_ECC_DE_TO_ESM_1_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_221 |
|
|
R5FSS0_COMMON0_ECC_SE_TO_ESM_0_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_212 |
|
|
R5FSS0_COMMON0_ECC_SE_TO_ESM_1_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_222 |
|
|
R5FSS0_COMMON0_SELFTEST_ERR_PULSE_OUT_0 |
ESM0_ESM_PLS_EVENT0_IN_232 |
|
|
R5FSS0_COMMON0_SELFTEST_ERR_PULSE_OUT_0 |
ESM0_ESM_PLS_EVENT1_IN_232 |
|
|
R5FSS0_COMMON0_SELFTEST_ERR_PULSE_OUT_0 |
ESM0_ESM_PLS_EVENT2_IN_232 |
|
|
R5FSS0_COMMON0_VIM_COMPARE_ERR_PULSE_OUT_0 |
ESM0_ESM_PLS_EVENT0_IN_233 |
|
|
R5FSS0_COMMON0_VIM_COMPARE_ERR_PULSE_OUT_0 |
ESM0_ESM_PLS_EVENT1_IN_233 |
|
|
R5FSS0_COMMON0_VIM_COMPARE_ERR_PULSE_OUT_0 |
ESM0_ESM_PLS_EVENT2_IN_233 |
|
|
R5FSS1 |
R5FSS1_CCM_COMPARE_STAT_PULSE_INTR_OUT_0 |
ESM0_ESM_PLS_EVENT0_IN_236 |
|
R5FSS1_CCM_COMPARE_STAT_PULSE_INTR_OUT_0 |
ESM0_ESM_PLS_EVENT1_IN_236 |
|
|
R5FSS1_CCM_COMPARE_STAT_PULSE_INTR_OUT_0 |
ESM0_ESM_PLS_EVENT2_IN_236 |
|
|
R5FSS1_CORE0 |
R5FSS1_CORE0_CTI_OUT_0 |
R5FSS1_CORE0_INTR_IN_175 |
|
R5FSS1_CORE0_CTI_OUT_0 |
R5FSS1_CORE1_INTR_IN_175 |
|
|
R5FSS1_CORE0_EXP_INTR_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_126 |
|
|
R5FSS1_CORE0_EXP_INTR_OUT_0 |
R5FSS1_CORE0_INTR_IN_4 |
|
|
R5FSS1_CORE0_PMU_OUT_0 |
R5FSS1_CORE0_INTR_IN_94 |
|
|
R5FSS1_CORE0_PMU_OUT_0 |
R5FSS1_CORE1_INTR_IN_94 |
|
|
R5FSS1_CORE0_VALFIQ_OUT_0 |
R5FSS1_CORE0_INTR_IN_95 |
|
|
R5FSS1_CORE0_VALIRQ_OUT_0 |
R5FSS1_CORE0_INTR_IN_96 |
|
|
R5FSS1_CORE1 |
R5FSS1_CORE1_CTI_OUT_0 |
R5FSS1_CORE0_INTR_IN_176 |
|
R5FSS1_CORE1_CTI_OUT_0 |
R5FSS1_CORE1_INTR_IN_176 |
|
|
R5FSS1_CORE1_EXP_INTR_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_127 |
|
|
R5FSS1_CORE1_EXP_INTR_OUT_0 |
R5FSS1_CORE1_INTR_IN_4 |
|
|
R5FSS1_CORE1_PMU_OUT_0 |
R5FSS1_CORE0_INTR_IN_93 |
|
|
R5FSS1_CORE1_PMU_OUT_0 |
R5FSS1_CORE1_INTR_IN_93 |
|
|
R5FSS1_CORE1_VALFIQ_OUT_0 |
R5FSS1_CORE1_INTR_IN_95 |
|
|
R5FSS1_CORE1_VALIRQ_OUT_0 |
R5FSS1_CORE1_INTR_IN_96 |
|
|
R5FSS1_CORE0_ECC_AGGR |
R5FSS1_CORE0_ECC_AGGR_ECC_CORRECTED_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_42 |
|
R5FSS1_CORE0_ECC_AGGR_ECC_UNCORRECTED_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_43 |
|
|
R5FSS1_CORE1_ECC_AGGR |
R5FSS1_CORE1_ECC_AGGR_ECC_CORRECTED_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_44 |
|
R5FSS1_CORE1_ECC_AGGR_ECC_UNCORRECTED_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_45 |
|
|
R5FSS1_COMMON0 |
R5FSS1_COMMON0_BUS_MONITOR_ERR_PULSE_OUT_0 |
ESM0_ESM_PLS_EVENT0_IN_235 |
|
R5FSS1_COMMON0_BUS_MONITOR_ERR_PULSE_OUT_0 |
ESM0_ESM_PLS_EVENT1_IN_235 |
|
|
R5FSS1_COMMON0_BUS_MONITOR_ERR_PULSE_OUT_0 |
ESM0_ESM_PLS_EVENT2_IN_235 |
|
|
R5FSS1_COMMON0_COMMRX_LEVEL_0_OUT_0 |
R5FSS1_CORE0_INTR_IN_5 |
|
|
R5FSS1_COMMON0_COMMRX_LEVEL_1_OUT_0 |
R5FSS1_CORE1_INTR_IN_5 |
|
|
R5FSS1_COMMON0_COMMTX_LEVEL_0_OUT_0 |
R5FSS1_CORE0_INTR_IN_6 |
|
|
R5FSS1_COMMON0_COMMTX_LEVEL_1_OUT_0 |
R5FSS1_CORE1_INTR_IN_6 |
|
|
R5FSS1_COMMON0_COMPARE_ERR_PULSE_OUT_0 |
ESM0_ESM_PLS_EVENT0_IN_237 |
|
|
R5FSS1_COMMON0_COMPARE_ERR_PULSE_OUT_0 |
ESM0_ESM_PLS_EVENT1_IN_237 |
|
|
R5FSS1_COMMON0_COMPARE_ERR_PULSE_OUT_0 |
ESM0_ESM_PLS_EVENT2_IN_237 |
|
|
R5FSS1_COMMON0_ECC_DE_TO_ESM_0_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_46 |
|
|
R5FSS1_COMMON0_ECC_DE_TO_ESM_1_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_47 |
|
|
R5FSS1_COMMON0_ECC_SE_TO_ESM_0_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_48 |
|
|
R5FSS1_COMMON0_ECC_SE_TO_ESM_1_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_49 |
|
|
R5FSS1_COMMON0_SELFTEST_ERR_PULSE_OUT_0 |
ESM0_ESM_PLS_EVENT0_IN_238 |
|
|
R5FSS1_COMMON0_SELFTEST_ERR_PULSE_OUT_0 |
ESM0_ESM_PLS_EVENT1_IN_238 |
|
|
R5FSS1_COMMON0_SELFTEST_ERR_PULSE_OUT_0 |
ESM0_ESM_PLS_EVENT2_IN_238 |
|
|
R5FSS1_COMMON0_VIM_COMPARE_ERR_PULSE_OUT_0 |
ESM0_ESM_PLS_EVENT0_IN_239 |
|
|
R5FSS1_COMMON0_VIM_COMPARE_ERR_PULSE_OUT_0 |
ESM0_ESM_PLS_EVENT1_IN_239 |
|
|
R5FSS1_COMMON0_VIM_COMPARE_ERR_PULSE_OUT_0 |
ESM0_ESM_PLS_EVENT2_IN_239 |
| Instance | OUT Interrupt | Connected To |
|---|---|---|
|
WKUP_R5FSS0_CORE0 |
WKUP_R5FSS0_CORE0_CTI_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_175 |
|
WKUP_R5FSS0_CORE0_ECC_CORRECTED_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_30 |
|
|
WKUP_R5FSS0_CORE0_ECC_UNCORRECTED_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_91 |
|
|
WKUP_R5FSS0_CORE0_EXP_INTR_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_124 |
|
|
WKUP_R5FSS0_CORE0_EXP_INTR_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_4 |
|
|
WKUP_R5FSS0_CORE0_PMU_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_58 |
|
|
WKUP_R5FSS0_CORE0_VALFIQ_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_59 |
|
|
WKUP_R5FSS0_CORE0_VALIRQ_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_60 |
|
|
WKUP_R5FSS0_COMMON0 |
WKUP_R5FSS0_COMMON0_COMMRX_LEVEL_0_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_5 |
|
WKUP_R5FSS0_COMMON0_COMMTX_LEVEL_0_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_6 |
|
|
WKUP_R5FSS0_COMMON0_ECC_DE_TO_ESM_0_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_40 |
|
|
WKUP_R5FSS0_COMMON0_ECC_SE_TO_ESM_0_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_41 |