ADS5296A
- Configurable Modes of Operation:
- 10-Bit, 200-MSPS, 4-Channel ADC
- 12-Bit, 160-MSPS, 4-Channel ADC
- 10-Bit, 100-MSPS, 8-Channel ADC
- 12-Bit, 80-MSPS, 8-Channel ADC
- Designed for Low Power:
- 65 mW per Channel at 80 MSPS
(12-Bit, 8-Channel) - 150 mW per Channel at 200 MSPS
(10-Bit, 4-Channel)
- 65 mW per Channel at 80 MSPS
- 12-Bit, 80 MSPS:
- SNR: 70.3 dBFS
- 10-Bit, 200 MSPS:
- SNR: 61.3 dBFS
- Interleaving Spur: > 60 dBc at 90 MHz
- Serial LVDS One-Wire Interface:
- 10x Serialization up to 1000 Mbps Data Rate per Wire
- 12x Serialization up to 960 Mbps Data Rate per Wire
- Digital Processing Block:
- Programmable FIR Decimation Filter and Oversampling to Minimize Harmonic Interference
- Programmable IIR High-Pass Filter to Minimize DC Offset
- Programmable Digital Gain: 0 dB to 12 dB
- Low-Frequency Noise Suppression Mode
- Programmable Mapping Between ADC Input Channels and LVDS Output Pins
- Channel Averaging Mode
- Variety of LVDS Test Patterns to Verify
Data Capture by FPGA or Receiver - Package: 9-mm × 9-mm QFN-64
The ADS5296A is a low-power, 12-bit, 8-channel, analog-to-digital converter (ADC) with sample rates up to 80 MSPS. However, the device can also be configured to operate as a 4-channel ADC running at 2x the sample rate by interleaving data from two ADC channels. In interleaving mode, the device accepts a double frequency input clock. Each ADC in a pair converts a common analog input signal at alternate rising edges of the 2x input clock. The device can either be configured as a 10-bit, 4-channel ADC with sample rates up to 200 MSPS or as a 12-bit, 4-channel ADC with sample rates up to 160 MSPS.
The data from each ADC within the interleaved pair is output in serial format over one LVDS pair up to a maximum data rate of 1 Gbps (10 bits at 100 MSPS). With interleaving disabled, the ADS5296A can also be operated as an 8-channel, 10-bit device with sample rates up to 100 MSPS.
Several digital functions commonly used in systems are included in the device. These functions include a low-frequency noise suppression (LFNS) mode, digital filtering options, and programmable mapping of LVDS output pins and analog input channels.
For low input frequency applications, the LFNS mode enables the suppression of noise at low frequencies and improves SNR in the 1-MHz band near dc by approximately 3 dB. Digital filtering options include low-pass, high-pass, and band-pass digital filters as well as dc offset removal filters.
Low power consumption and integration of multiple channels in a small package makes the device attractive for high channel count data acquisition systems. The device is available in a compact 9-mm × 9-mm QFN-64 package. The ADS5296A is specified over the –40°C to +85°C operating temperature range.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | 10-Bit, 200-MSPS, 4-Channel and 12-Bit, 80-MSPS, 8-Channel ADC . datasheet | 2013. 10. 30 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
SLAC547 — ADS5295 and ADS5296 GUI Installer, v2.1
ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
아날로그 엔지니어의 계산기는 아날로그 회로 설계 엔지니어가 정기적으로 사용하는 많은 반복 계산의 속도를 높이도록 설계되었습니다. 이 PC 기반 툴은 피드백 저항을 사용한 연산 증폭기 게인 설정부터 아날로그-디지털 컨버터(ADC) 드라이브 버퍼 회로 안정화를 위한 적절한 회로 설계 요소 선택에 이르기까지 다양한 일반적인 계산 목록이 포함된 그래픽 인터페이스를 제공합니다.
이 계산기는 독립 실행형 툴로 유용할 뿐만 아니라 아날로그 엔지니어의 포켓 레퍼런스에 설명된 개념과도 잘 어울립니다.
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| VQFN (RGC) | 64 | Ultra Librarian |
주문 및 품질
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.