The ADS54J40 is a low-power, wide-bandwidth, 14-bit, 1.0-GSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –158 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10.0 Gbps, supporting two or four lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. Each ADC channel optionally can be connected to a wideband digital down-converter (DDC) block. The ADS54J40 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption.
The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 14-bit data from each channel.
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| 상위 문서 | 유형 | 직함 | 형식 옵션 | 날짜 |
|---|---|---|---|---|
| * | Data sheet | ADS54J40 Dual-Channel, 14-Bit, 1.0-GSPS Analog-to-Digital Converter datasheet (Rev. C) | 2018/01/09 |
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
ADS54J40EVM은 텍사스 인스트루먼트의 ADS54J40 및 LMK04828 클록 지터 클리너를 평가할 수 있는 평가 모듈(EVM)입니다. ADS54J40은 JESD204B 인터페이스를 포함하고 버퍼 아날로그 입력 및 출력을 지원하는 저전력, 14비트, 1 GSPS ADC(아날로그-디지털 컨버터)입니다. 이 EVM에는 광범위한 신호 소스 및 주파수를 수용할 수 있는 변압기 결합 아날로그 입력이 있습니다. LMK04828은 시스템 레퍼런스 클록 및 디바이스 샘플 클록과 함께 초저지터 및 위상 잡음 ADC 샘플 클록이 포함되어 (...)
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)
The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| VQFNP (RMP) | 72 | Ultra Librarian |
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.
Analog Engineer's Calc Installer
General calculator tool for analog design support.
The design resource accessed as www.ti.com/lit/zip/slwc107 or www.ti.com/lit/xx/slwc107w/slwc107w.zip has been migrated to a new user experience at www.ti.com/tool/download/SLWC107. Please update any bookmarks accordingly.