제품 상세 정보

Sample rate (max) (Msps) 100 Resolution (Bits) 14, 16, 18 Number of input channels 4 Interface type Parallel LVDS Analog input BW (MHz) 70 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 4 Power consumption (typ) (mW) 1350 Architecture Pipeline SNR (dB) 85.5 ENOB (Bits) 12.8 SFDR (dB) 81 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 100 Resolution (Bits) 14, 16, 18 Number of input channels 4 Interface type Parallel LVDS Analog input BW (MHz) 70 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 4 Power consumption (typ) (mW) 1350 Architecture Pipeline SNR (dB) 85.5 ENOB (Bits) 12.8 SFDR (dB) 81 Operating temperature range (°C) -40 to 85 Input buffer No
VQFN (RGC) 64 81 mm² 9 x 9
  • Maximum Sample Rate: 100 MSPS
  • Programmable Device Resolution
    • Quad-Channel, 16-Bit, High-SNR Mode
    • Quad-Channel, 14-Bit, Low-Power Mode
  • 16-Bit High-SNR Mode
    • 1.4 W Total Power at 100 MSPS
      • 355 mW / Channel
    • 4 Vpp Full-scale Input
    • 85-dBFS SNR at fin = 3 MHz, 100 MSPS
  • 14-Bit Low-Power Mode
    • 785 mW Total Power at 100 MSPS
      • 195 mW/Channel
    • 2-Vpp Full-Scale Input
    • 74-dBFS SNR at fin = 10 MHz
    • Integrated Clamp (for interfacing to
      CCD sensors)
  • Low-Frequency Noise Suppression
  • Digital Processing Block
    • Programmable FIR Decimation Filters
    • Programmable Digital Gain: 0 dB to 12 dB
    • 2- or 4-Channel Averaging
  • Programmable Mapping Between ADC Input
    Channels and LVDS Output Pins–Eases Board
    Design
  • Variety of Test Patterns to Verify Data Capture by
    FPGA/Receiver
  • Serialized LVDS Outputs
  • Internal and External References
  • 3.3-V Analog Supply
  • 1.8-V Digital Supply
  • Recovers From 6-dB Overload Within 1 Clock
    Cycle
  • Package:
    • 9-mm × 9-mm 64-Pin QFN
    • Non-Magnetic Package Option for MRI
      Systems
  • CMOS Technology
  • Maximum Sample Rate: 100 MSPS
  • Programmable Device Resolution
    • Quad-Channel, 16-Bit, High-SNR Mode
    • Quad-Channel, 14-Bit, Low-Power Mode
  • 16-Bit High-SNR Mode
    • 1.4 W Total Power at 100 MSPS
      • 355 mW / Channel
    • 4 Vpp Full-scale Input
    • 85-dBFS SNR at fin = 3 MHz, 100 MSPS
  • 14-Bit Low-Power Mode
    • 785 mW Total Power at 100 MSPS
      • 195 mW/Channel
    • 2-Vpp Full-Scale Input
    • 74-dBFS SNR at fin = 10 MHz
    • Integrated Clamp (for interfacing to
      CCD sensors)
  • Low-Frequency Noise Suppression
  • Digital Processing Block
    • Programmable FIR Decimation Filters
    • Programmable Digital Gain: 0 dB to 12 dB
    • 2- or 4-Channel Averaging
  • Programmable Mapping Between ADC Input
    Channels and LVDS Output Pins–Eases Board
    Design
  • Variety of Test Patterns to Verify Data Capture by
    FPGA/Receiver
  • Serialized LVDS Outputs
  • Internal and External References
  • 3.3-V Analog Supply
  • 1.8-V Digital Supply
  • Recovers From 6-dB Overload Within 1 Clock
    Cycle
  • Package:
    • 9-mm × 9-mm 64-Pin QFN
    • Non-Magnetic Package Option for MRI
      Systems
  • CMOS Technology

Using CMOS process technology and innovative circuit techniques, the ADS5263 is designed to operate at low power and give very high SNR performance with a 4-Vpp full-scale input. Using a low-noise 16-bit front-end stage followed by a 14-bit ADC, the device gives 85-dBFS SNR up to 10 MHz and better than 80-dBFS SNR up to 30 MHz.

ADS5263 has a 14-bit low power mode, where it operates as a quad-channel 14-bit ADC. The 16-bit front-end stage is powered down and the part consumes almost half the power, compared to the 16-bit mode. The 14-bit mode supports a 2-Vpp full-scale input signal, with typical 74-dBFS SNR. The ADS5263 can be dynamically switched between the two resolution modes. This allows systems to use the same part in a high-resolution, high-power mode or a low-resolution, low-power mode.

The device also has a digital processing block that integrates several commonly used digital functions, such as digital gain (up to 12 dB). It includes a digital filter module that has built-in decimation filters (with low-pass, high-pass and band-pass characteristics). The decimation rate is also programmable (by 2, by 4, or by 8). This makes it very useful for narrow-band applications, where the filters can be used to improve SNR and knock-off harmonics, while at the same time reducing the output data rate.

The device includes an averaging mode where two channels (or even four channels) can be averaged to improve SNR. A very unique feature is the programmable mapper module that allows flexible mapping between the input channels and the LVDS output pins. This helps to greatly reduce the complexity of LVDS output routing and can potentially result in cheaper system boards by reducing the number of PCB layers. Specification of device is over industrial temperature range of –40°C to 85°C.

Using CMOS process technology and innovative circuit techniques, the ADS5263 is designed to operate at low power and give very high SNR performance with a 4-Vpp full-scale input. Using a low-noise 16-bit front-end stage followed by a 14-bit ADC, the device gives 85-dBFS SNR up to 10 MHz and better than 80-dBFS SNR up to 30 MHz.

ADS5263 has a 14-bit low power mode, where it operates as a quad-channel 14-bit ADC. The 16-bit front-end stage is powered down and the part consumes almost half the power, compared to the 16-bit mode. The 14-bit mode supports a 2-Vpp full-scale input signal, with typical 74-dBFS SNR. The ADS5263 can be dynamically switched between the two resolution modes. This allows systems to use the same part in a high-resolution, high-power mode or a low-resolution, low-power mode.

The device also has a digital processing block that integrates several commonly used digital functions, such as digital gain (up to 12 dB). It includes a digital filter module that has built-in decimation filters (with low-pass, high-pass and band-pass characteristics). The decimation rate is also programmable (by 2, by 4, or by 8). This makes it very useful for narrow-band applications, where the filters can be used to improve SNR and knock-off harmonics, while at the same time reducing the output data rate.

The device includes an averaging mode where two channels (or even four channels) can be averaged to improve SNR. A very unique feature is the programmable mapper module that allows flexible mapping between the input channels and the LVDS output pins. This helps to greatly reduce the complexity of LVDS output routing and can potentially result in cheaper system boards by reducing the number of PCB layers. Specification of device is over industrial temperature range of –40°C to 85°C.

다운로드 스크립트와 함께 비디오 보기 비디오

기술 자료

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하세요.
7개 모두 보기
상위 문서 유형 직함 형식 옵션 날짜
* Data sheet ADS5263 Quad Channel 16-Bit, 100-MSPS High-SNR ADC datasheet (Rev. D) PDF | HTML 2015/11/30
Application note High Speed ADCs and Amplifiers for Flow Cytometry Applications 2020/10/12
Application note Introduction to Magnetic Resonance Imaging (MRI) 2017/09/14
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 2015/05/22
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 2013/07/19
Application note Understanding Serial LVDS Capture in High-Speed ADCs 2013/07/10
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 2008/06/08

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

ADS5263EVM — ADS5263 평가 모듈

ADS5263은 최대 100MSPS 샘플링 주파수를 지원하는 4채널 16비트 ADC로, 10MHz 입력을 지원하는 84.6dBFS의 신호 대 잡음비(SNR)를 제공합니다. ADS5263 평가 모듈(EVM)은 다양한 클록 및 입력 조건에서 ADS5263을 테스트할 수 있는 유연한 환경을 제공합니다. 이 EVM을 사용하면 자체 필터를 설계하고, EVM에 해당 부품을 채우고, EVM 자체에서 성능을 확인할 수 있습니다.

ADS5263EVM 평가를 위해 TSW1400EVM(구형)이 필요합니다. TSW1400EVM이 이미 있는 경우가 (...)

사용 설명서: PDF
TI.com에서 구매할 수 없음
평가 모듈(EVM)용 GUI

SLAC476 ADS5263EVM GUI Installer v2.2

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

시뮬레이션 모델

ADS5263 IBIS Model

SLAM080.ZIP (26 KB) - IBIS Model
계산 툴

ANALOG-ENGINEER-CALC PC software analog engineer's calculator

The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

시뮬레이션 툴

PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®

TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 착수하기 (...)
패키지 CAD 기호, 풋프린트 및 3D 모델
VQFN (RGC) 64 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

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