The ADS58J64 is a low-power, wide-bandwidth, 14-bit, 1-GSPS, quad-channel, telecom receiver device. The ADS58J64 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS58J64 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to a 200-MHz receive bandwidth. The ADS58J64 also supports a 14-bit, 500-MSPS output in burst mode, making the device suitable for a digital pre-distortion (DPD) observation receiver.
The JESD204B interface reduces the number of interface lines, thus allowing high system integration density. An internal phase-locked loop (PLL) multiplies the incoming analog-to-digital converter (ADC) sampling clock to derive the bit clock that is used to serialize the 14-bit data from each channel.
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 날짜 |
|---|---|---|---|---|
| * | Data sheet | ADS58J64 Quad-Channel, 14-Bit, 1-GSPS Telecom Receiver Device datasheet (Rev. B) | PDF | HTML | 2021/12/21 |
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ADS58J64EVM은 텍사스 인스트루먼트의 ADS58J64 통합형 리시버 평가에 사용되는 평가 보드입니다. ADS58J64는 저전력 14비트, 500MSPS, 쿼드 채널 통신 리시버로 버퍼링된 아날로그 입력을 사용합니다. 이 장치는 JESD204B 인터페이스 및 최대 10Gbps의 데이터 전송률을 지원합니다. EVM에는 단일 종단 신호 및 클록 소스를 지원하고 다양한 신호 주파수를 수용할 수 있도록 변압기에 연결된 아날로그 및 클록 입력이 있습니다. 아날로그 입력에서는 더 우수한 진폭 및 위상 매칭 성능을 위해 변압기들이 앞뒤로 (...)
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)
The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| VQFN (RRH) | 72 | Ultra Librarian |
| VQFNP (RMP) | 72 | Ultra Librarian |
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.
Analog Engineer's Calc Installer
General calculator tool for analog design support.
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