Product details

Resolution (Bits) 16 Number of DAC channels (#) 4 Interface type JESD204B Sample/update rate (MSPS) 2500 Features Ultra High Speed Rating Catalog Interpolation 16x, 1x, 2x, 4x, 8x Power consumption (Typ) (mW) 1859 SFDR (dB) 81 Architecture Current Source Operating temperature range (C) -40 to 85 Reference type Int
Resolution (Bits) 16 Number of DAC channels (#) 4 Interface type JESD204B Sample/update rate (MSPS) 2500 Features Ultra High Speed Rating Catalog Interpolation 16x, 1x, 2x, 4x, 8x Power consumption (Typ) (mW) 1859 SFDR (dB) 81 Architecture Current Source Operating temperature range (C) -40 to 85 Reference type Int
FCBGA (AAV) 144 100 mm² 10 x 10
  • Resolution: 16-Bit
  • Maximum Sample Rate:
    • DAC37J84: 1.6 GSPS
    • DAC38J84: 2.5 GSPS
  • Maximum Input Data Rate: 1.23GSPS
  • JESD204B Interface
    • 8 JESD204B Serial Input Lanes
    • 12.5 Gbps Maximum Bit Rate per Lane
    • Subclass 1 Multi-DAC Synchronization
  • On-Chip Very Low Jitter PLL
  • Selectable 1x -16x Interpolation
  • Independent Complex Mixers with 48-bit NCO/
    or ±n×Fs/8
  • Wideband Digital Quadrature Modulator Correction
  • Sinx/x Correction Filters
  • Fractional Sample Group Delay Correction
  • Multi-Band Mode: Digital Summation of Independent
    Complex Signals
  • 3/4-Wire Serial Control Bus (SPI):1.5V – 1.8V
  • Integrated Temperature Sensor
  • JTAG Boundary Scan
  • Terminal-Compatible with Dual-Channel DAC37J82/
    DAC38J82 Family
  • Power Dissipation: 1.8W at 2.5GSPS
  • Package: 10x10mm, 144-Ball Flip-Chip BGA
  • Resolution: 16-Bit
  • Maximum Sample Rate:
    • DAC37J84: 1.6 GSPS
    • DAC38J84: 2.5 GSPS
  • Maximum Input Data Rate: 1.23GSPS
  • JESD204B Interface
    • 8 JESD204B Serial Input Lanes
    • 12.5 Gbps Maximum Bit Rate per Lane
    • Subclass 1 Multi-DAC Synchronization
  • On-Chip Very Low Jitter PLL
  • Selectable 1x -16x Interpolation
  • Independent Complex Mixers with 48-bit NCO/
    or ±n×Fs/8
  • Wideband Digital Quadrature Modulator Correction
  • Sinx/x Correction Filters
  • Fractional Sample Group Delay Correction
  • Multi-Band Mode: Digital Summation of Independent
    Complex Signals
  • 3/4-Wire Serial Control Bus (SPI):1.5V – 1.8V
  • Integrated Temperature Sensor
  • JTAG Boundary Scan
  • Terminal-Compatible with Dual-Channel DAC37J82/
    DAC38J82 Family
  • Power Dissipation: 1.8W at 2.5GSPS
  • Package: 10x10mm, 144-Ball Flip-Chip BGA

The terminal-compatible DAC37J84/DAC38J84 family is a low power, 16-bit, quad-channel, 1.6/2.5 GSPS digital to analog converter (DAC) with JESD204B interface.

Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices.

The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement.

A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (QDC) enable complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the abnormal power behavior of the input data is detected.

The terminal-compatible DAC37J84/DAC38J84 family is a low power, 16-bit, quad-channel, 1.6/2.5 GSPS digital to analog converter (DAC) with JESD204B interface.

Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices.

The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement.

A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (QDC) enable complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the abnormal power behavior of the input data is detected.

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Technical documentation

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Type Title Date
* Data sheet Quad-Channel, 16-Bit, 1.6/2.5 GSPS, Digital-to-Analog Converters datasheet (Rev. B) 24 Mar 2014
Technical article Keys to quick success using high-speed data converters 13 Oct 2020
Application note DAC3xJ8x Device Initialization and SYSREF Configuration 27 Sep 2017
Technical article Digital signal processing in RF sampling DACs – part 2 04 Apr 2017
Technical article Digital signal processing in RF sampling DACs - part 1 13 Feb 2017
Technical article Why phase noise matters in RF sampling converters 28 Nov 2016
User guide TSW14J10 FMC-USB Interposer Card User's Guide (Rev. B) 28 Sep 2016
Design guide Wideband Receiver With 66AK2L06 JESD204B Attach to ADC32RF80 Reference Design 23 Sep 2016
Application note 66AK2L06 JESD Attach to ADC12J4000/DAC38J84 Getting Started Guide (Rev. B) 20 Jun 2016
User guide DAC3XJ8XEVM User's Guide (Rev. B) 28 Apr 2016
User guide TSW14J50 User's Guide (Rev. A) 25 Apr 2016
User guide TSW3XJ8XEVM User's Guide (Rev. B) 09 Mar 2016
User guide TSW14J56 JESD204B High-Speed Data Capture/ Pattern Generator Card User's Guide (Rev. C) 11 Jan 2016
Design guide 66AK2L06 JESD Attach to ADC12J4000 / DAC38J84 Design Guide (Rev. A) 22 Oct 2015
Application note System solution for avionics & defense 23 Sep 2015
White paper Ready to make the jump to JESD204B? White Paper (Rev. B) 19 Mar 2015
User guide Altera JESD204B IP Core and TI DAC37J84 Hardware Checkout Report (Rev. A) 15 Sep 2014
Design guide Analog Interfacing Networks for DAC348x and Modulators (TIDA-00077) (Rev. A) 14 Aug 2013
Application note High Speed, Digital-to-Analog Converters Basics (Rev. A) 23 Oct 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

DAC38J84EVM — DAC38J84 Quad-Channel, 16-Bit, 2.5-GSPS, 1x-16x Interpolating DAC Evaluation Module

 The DAC3XJ8XEVM is an evaluation module (EVM) designed to evaluate the DAC3XJ8X family of high-speed, JESD204B interface DACs (DAC37J82, DAC37J84, DAC38J82, DAC38J84). The EVM includes an onboard clocking solution (LMK04828), transformer coupled outputs, full power solution, and easy-to-use software (...)

In stock
Limit: 2
Evaluation board

TSW38J84EVM — TSW38J84 Evaluation Module

The TSW38J84EVM Evaluation Module is an evaluation board that allows system designers to evaluate the performance of Texas Instruments' dual transmit signal chain consisting of the DAC38J84, TRF3722, TRF3705, and the LMK04828. For ease of use as a complete dual RF transmit solution the TSW38J84EVM (...)

In stock
Limit: 3
Firmware

TI-JESD204-IP — JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
Firmware

TSW14J10EVM Xilinx Firmware Source (Rev. C)

SLAC690C.ZIP (5251 KB)
GUI for evaluation module (EVM)

DAC3XJ8XEVM Software (Rev. B)

SLAC644B.ZIP (219583 KB)
GUI for evaluation module (EVM)

TSW3xJ8xEVM Software

SLAC661.ZIP (182158 KB)
GUI for evaluation module (EVM)

High Speed Data Converter Pro GUI Installer, v5.20 (Rev. W)

SLWC107W.ZIP (591961 KB)
Support software

DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards (...)
Simulation model

DAC38J84 IBIS Model

SLAM197.ZIP (50 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
参考设计

TIDA-00409 — 1-GHz Bandwidth Dual Channel Transmitter up to 4-GHz Reference Design

The TSW38J84 EVM reference design provides a platform to demonstrate a wideband dual transmit solution that incorporates an integrated LO.  The reference design utilizes the 2.5 GSPS DAC38J84 device with the high performance modulators: TRF3722 (including integrated PLL/VCO) and TRF3705. The (...)
参考设计

TIDA-00996 — Synchronized Multi-Transmitter Reference Design: Method of Time-Aligning Multiple DACs

To further increase the range, data rate, and reliability of modern mobile communications systems, system designers continue to place more emphasis on multiple-antenna transmitter systems to achieve combinations of spatial diversity and spatial multiplexing. Such implementations can further (...)
参考设计

TIDEP0060 — Optimized Radar System Reference Design Using a DSP+ARM SoC

For modern radar system developers currently using an FPGA or ASIC to connect to high speed data converters, who need faster time to market with increased performance and significant reduction in cost, power, and size, this reference design includes the first widely available processor integrating a (...)
参考设计

TIDA-00684 — High-Bandwidth Arbitrary Waveform Generator Reference Design: DC or AC coupled, High-Voltage output

In TIDA-00684 reference design a quad-channel TSW3080 evaluation module (EVM) is developed to shows how to use an active amplifier interface with the DAC38J84 to demonstrate an arbitrary-waveform-generator frontend. The DAC38J84 provides four DAC channels with 16 bits of resolution with a maximum (...)
参考设计

TIDEP0081 — Wideband Receiver Design Using 66AK2L06 JESD204B Attach to ADC32RF80 Reference Design

For wideband receiver system developers currently using FPGA or ASIC to connect High Speed data converters to a baseband processor, who need faster time to market with increased performance and significant reduction in cost, power, and size. This reference design includes the first widely available (...)
参考设计

TIDEP0034 — 66AK2L06 DSP+ARM Processor with JESD204B Attach to Wideband ADCs and DACs

For developers currently using an FPGA or ASIC to connect to high speed data converters who need faster time to market with increased performance and significant reduction in cost, power, and size this reference design includes the first widely available processor integrating a JESD204B interface (...)
参考设计

TIDA-00335 — High Bandwidth, High Frequency Transmitter Reference Design

This design illustrates the circuit modifications required to support high bandwidth and  high frequency applications using current source DACs like the  DAC38J84 with the TRF3704 modulator.  The TRF3704 is a 6 GHz modulator capable of supporting wide BB bandwidths.  The DAC38J84 (...)
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FCBGA (AAV) 144 View options

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