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AM6412

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Dual-core 64-bit Arm® Cortex®-A53, single-core Cortex-R5F, PCIe, USB 3.0 and security

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AM6412

ACTIVE
Data sheet Order now

Product details

Arm CPU 2 Arm Cortex-A53 Arm (max) (MHz) 800, 1000 Coprocessors 1 Arm Cortex-R5F CPU 64-bit Protocols Ethernet, TSN Ethernet MAC 2-Port 10/100/1000 PCIe 1 PCIe Gen 2 Hardware accelerators PRU-ICSSG, Security Accelerator Features Networking Operating system Linux, RTOS Security Cryptography, Debug security, Secure boot, Trusted execution environment Rating Catalog Power supply solution TPS65219, TPS65220 Operating temperature range (°C) -40 to 105
Arm CPU 2 Arm Cortex-A53 Arm (max) (MHz) 800, 1000 Coprocessors 1 Arm Cortex-R5F CPU 64-bit Protocols Ethernet, TSN Ethernet MAC 2-Port 10/100/1000 PCIe 1 PCIe Gen 2 Hardware accelerators PRU-ICSSG, Security Accelerator Features Networking Operating system Linux, RTOS Security Cryptography, Debug security, Secure boot, Trusted execution environment Rating Catalog Power supply solution TPS65219, TPS65220 Operating temperature range (°C) -40 to 105
FCBGA (ALV) 441 295.84 mm² 17.2 x 17.2

Processor cores:

  • 1× Dual 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.0GHz
    • Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC
    • Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
  • Up to 2× Dual-core Arm Cortex-R5F MCU subsystems at up to 800MHz, integrated for real-time processing
    • Dual-core Arm Cortex-R5F supports dual-core and single-core modes
    • 32KB ICache, 32KB DCache and 64KB TCM per each R5F core for a total of 256KB TCM with SECDED ECC on all memories
  • 1× Single-core Arm Cortex-M4F MCU at up to 400MHz
    • 256KB SRAM with SECDED ECC

Industrial subsystem:

  • 2× gigabit Industrial Communication Subsystems (PRU_ICSSG)
    • Supports Profinet IRT, Profinet RT, EtherNet/IP, EtherCAT, Time-Sensitive Networking (TSN), and more
    • Backward compatibility with 10/100Mb PRU_ICSS
    • Each PRU_ICSSG contains:
      • 2× Ethernet ports
        • MII (10/100)
        • RGMII (10/100/1000)
      • 6 PRU RISC cores per PRU_ICSSG each core having:
        • Instruction RAM with ECC
        • Broadside RAM
        • Multiplier with optional accumulator (MAC)
        • CRC16/32 hardware accelerator
        • Byte swap for Big/Little Endian conversion
        • SUM32 hardware accelerator for UDP checksum
        • Task Manager for preemption support
      • Three Data RAMs with ECC
      • 8 banks of 30 × 32-bit register scratchpad memory
      • Interrupt controller and task manager
      • Two 64-bit Industrial Ethernet Peripherals (IEPs) for time stamping and other time synchronization functions
      • 18× Sigma-Delta filters
        • Short circuit logic
        • Over-current logic
      • 6× Multi-protocol position encoder interfaces
      • One Enhanced Capture Module (ECAP)
      • 16550-compatible UART with a dedicated 192-MHz clock to support 12-Mbps PROFIBUS

Memory subsystem:

  • Up to 2MB of On-chip RAM (OCSRAM) with SECDED ECC:
    • Can be divided into smaller banks in increments of 256KB for as many as 8 separate memory banks
    • Each memory bank can be allocated to a single core to facilitate software task partitioning
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4, DDR4 memory types
    • 16-Bit data bus with inline ECC
    • Supports speeds up to 1600MT/s
  • 1× General-Purpose Memory Controller (GPMC)
    • 16-Bit parallel bus with 133-MHz clock or
    • 32-Bit parallel bus with 100-MHz clock
    • Error Location Module (ELM) support

System on Chip (SoC) Services:

  • Device Management Security Controller (DMSC-L)
    • Centralized SoC system controller
    • Manages system services including initial boot, security, and clock/reset/power management
    • Communication with various processing units over message manager
    • Simplified interface for optimizing unused peripherals

  • Data Movement Subsystem (DMSS)

    • Block Copy DMA (BCDMA)
    • Packet DMA (PKTDMA)
    • Secure Proxy (SEC_PROXY)
    • Ring Accelerator (RINGACC)

Security:

  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Secure watchdog/timer/IPC
    • Extensive firewall support for isolation
    • Secure storage support
    • Replay Protected Memory Block (RPMB) support
  • Security co-processor (DMSC-L) for key and security management, with dedicated device level interconnect for security
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
      • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging

High-speed interfaces:

  • 1× Integrated Ethernet switch (CPSW3G) supporting:
    • Up to 2 Ethernet ports
      • RMII (10/100)
      • RGMII (10/100/1000)
    • IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
    • Clause 45 MDIO PHY management
    • Energy efficient Ethernet (802.3az)
  • 1× PCI-Express Gen2 controller (PCIE)
    • Supports Gen2 operation
    • Supports Single Lane operation
  • 1× USB 3.1 Dual-Role Device (DRD) Subsystem (USBSS)
    • Port configurable as USB host,USB device, orUSB Dual-Role device
    • USB device: High-speed (480Mbps), andFull-speed (12Mbps)
    • USB host: SuperSpeed Gen 1 (5Gbps),High-speed (480Mbps),Full-speed (12Mbps), andLow-speed (1.5Mbps)

General connectivity:

  • 6× Inter-Integrated Circuit (I2C) ports
  • 9× configurable Universal Asynchronous Receive/Transmit (UART) modules
  • 1× Flash Subsystem (FSS) that can be configured as Octal SPI (OSPI) flash interfaces or one Quad SPI (QSPI)
  • 1× 12-Bit Analog-to-Digital Converters (ADC)
    • Up to 4MSPS
    • 8× multiplexed analog inputs
  • 7× Multichannel Serial Peripheral Interfaces (MCSPI) controllers
  • 6× Fast Serial Interface Receiver (FSI_RX) cores
  • 2× Fast Serial Interface Transmitter (FSI_TX) cores
  • 3× General-Purpose I/O (GPIO) modules

Control interfaces:

  • 9× Enhanced Pulse-Width Modulator (EPWM) modules
  • 3× Enhanced Capture (ECAP) modules
  • 3× Enhanced Quadrature Encoder Pulse (EQEP) modules
  • 2× Modular Controller Area Network (MCAN) modules with or without full CAN-FD support

Media and data storage:

  • 2× Multi-Media Card/Secure Digital (MMC/SD/SDIO) interfaces
    • One 4-bit for SD/SDIO;
    • One 8-bit for eMMC
    • Integrated analog switch for voltage switching between 3.3V to 1.8V for high-speed cards

Power management:

  • Simplified power sequence
  • Integrated SDIO LDO for handling automatic voltage transition for SD interface
  • Integrated voltage supervisor for safety monitoring of over-under voltage conditions
  • Integrated power supply glitch detector for detecting fast supply transients

Functional Safety:

  • Functional Safety-Compliant
    • Developed for functional safety applications
    • Documentation available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3
    • Hardware integrity up to SIL 2
    • Safety-related certification
  • Functional Safety Features
    • ECC or parity on calculation-critical memories
    • ECC and parity on select internal bus interconnect
    • Built-In Self-Test (BIST) for CPU and on-chip RAM
    • Error Signaling Module (ESM) with error pin
    • Runtime safety diagnostics, voltage, temperature, and clock monitoring, windowed watchdog timers, CRC engine for memory integrity checks
    • Dedicated MCU domain memory, interfaces, and M4F core capable of being isolated from the larger SoC with Freedom From Interference (FFI) features
      • Separate interconnect
      • Firewalls and timeout gaskets
      • Dedicated PLL
      • Dedicated I/O supply
      • Separate reset

SoC architecture:

  • Supports primary boot from UART, I2C, OSPI/QSPI Flash, SPI Flash, parallel NOR Flash, parallel NAND Flash, SD, eMMC, USB, PCIe, and Ethernet interfaces
  • 16-nm FinFET technology
  • 17.2mm × 17.2mm, 0.8-mm pitch, 441-pin BGA package

Processor cores:

  • 1× Dual 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.0GHz
    • Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC
    • Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
  • Up to 2× Dual-core Arm Cortex-R5F MCU subsystems at up to 800MHz, integrated for real-time processing
    • Dual-core Arm Cortex-R5F supports dual-core and single-core modes
    • 32KB ICache, 32KB DCache and 64KB TCM per each R5F core for a total of 256KB TCM with SECDED ECC on all memories
  • 1× Single-core Arm Cortex-M4F MCU at up to 400MHz
    • 256KB SRAM with SECDED ECC

Industrial subsystem:

  • 2× gigabit Industrial Communication Subsystems (PRU_ICSSG)
    • Supports Profinet IRT, Profinet RT, EtherNet/IP, EtherCAT, Time-Sensitive Networking (TSN), and more
    • Backward compatibility with 10/100Mb PRU_ICSS
    • Each PRU_ICSSG contains:
      • 2× Ethernet ports
        • MII (10/100)
        • RGMII (10/100/1000)
      • 6 PRU RISC cores per PRU_ICSSG each core having:
        • Instruction RAM with ECC
        • Broadside RAM
        • Multiplier with optional accumulator (MAC)
        • CRC16/32 hardware accelerator
        • Byte swap for Big/Little Endian conversion
        • SUM32 hardware accelerator for UDP checksum
        • Task Manager for preemption support
      • Three Data RAMs with ECC
      • 8 banks of 30 × 32-bit register scratchpad memory
      • Interrupt controller and task manager
      • Two 64-bit Industrial Ethernet Peripherals (IEPs) for time stamping and other time synchronization functions
      • 18× Sigma-Delta filters
        • Short circuit logic
        • Over-current logic
      • 6× Multi-protocol position encoder interfaces
      • One Enhanced Capture Module (ECAP)
      • 16550-compatible UART with a dedicated 192-MHz clock to support 12-Mbps PROFIBUS

Memory subsystem:

  • Up to 2MB of On-chip RAM (OCSRAM) with SECDED ECC:
    • Can be divided into smaller banks in increments of 256KB for as many as 8 separate memory banks
    • Each memory bank can be allocated to a single core to facilitate software task partitioning
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4, DDR4 memory types
    • 16-Bit data bus with inline ECC
    • Supports speeds up to 1600MT/s
  • 1× General-Purpose Memory Controller (GPMC)
    • 16-Bit parallel bus with 133-MHz clock or
    • 32-Bit parallel bus with 100-MHz clock
    • Error Location Module (ELM) support

System on Chip (SoC) Services:

  • Device Management Security Controller (DMSC-L)
    • Centralized SoC system controller
    • Manages system services including initial boot, security, and clock/reset/power management
    • Communication with various processing units over message manager
    • Simplified interface for optimizing unused peripherals

  • Data Movement Subsystem (DMSS)

    • Block Copy DMA (BCDMA)
    • Packet DMA (PKTDMA)
    • Secure Proxy (SEC_PROXY)
    • Ring Accelerator (RINGACC)

Security:

  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Secure watchdog/timer/IPC
    • Extensive firewall support for isolation
    • Secure storage support
    • Replay Protected Memory Block (RPMB) support
  • Security co-processor (DMSC-L) for key and security management, with dedicated device level interconnect for security
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
      • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging

High-speed interfaces:

  • 1× Integrated Ethernet switch (CPSW3G) supporting:
    • Up to 2 Ethernet ports
      • RMII (10/100)
      • RGMII (10/100/1000)
    • IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
    • Clause 45 MDIO PHY management
    • Energy efficient Ethernet (802.3az)
  • 1× PCI-Express Gen2 controller (PCIE)
    • Supports Gen2 operation
    • Supports Single Lane operation
  • 1× USB 3.1 Dual-Role Device (DRD) Subsystem (USBSS)
    • Port configurable as USB host,USB device, orUSB Dual-Role device
    • USB device: High-speed (480Mbps), andFull-speed (12Mbps)
    • USB host: SuperSpeed Gen 1 (5Gbps),High-speed (480Mbps),Full-speed (12Mbps), andLow-speed (1.5Mbps)

General connectivity:

  • 6× Inter-Integrated Circuit (I2C) ports
  • 9× configurable Universal Asynchronous Receive/Transmit (UART) modules
  • 1× Flash Subsystem (FSS) that can be configured as Octal SPI (OSPI) flash interfaces or one Quad SPI (QSPI)
  • 1× 12-Bit Analog-to-Digital Converters (ADC)
    • Up to 4MSPS
    • 8× multiplexed analog inputs
  • 7× Multichannel Serial Peripheral Interfaces (MCSPI) controllers
  • 6× Fast Serial Interface Receiver (FSI_RX) cores
  • 2× Fast Serial Interface Transmitter (FSI_TX) cores
  • 3× General-Purpose I/O (GPIO) modules

Control interfaces:

  • 9× Enhanced Pulse-Width Modulator (EPWM) modules
  • 3× Enhanced Capture (ECAP) modules
  • 3× Enhanced Quadrature Encoder Pulse (EQEP) modules
  • 2× Modular Controller Area Network (MCAN) modules with or without full CAN-FD support

Media and data storage:

  • 2× Multi-Media Card/Secure Digital (MMC/SD/SDIO) interfaces
    • One 4-bit for SD/SDIO;
    • One 8-bit for eMMC
    • Integrated analog switch for voltage switching between 3.3V to 1.8V for high-speed cards

Power management:

  • Simplified power sequence
  • Integrated SDIO LDO for handling automatic voltage transition for SD interface
  • Integrated voltage supervisor for safety monitoring of over-under voltage conditions
  • Integrated power supply glitch detector for detecting fast supply transients

Functional Safety:

  • Functional Safety-Compliant
    • Developed for functional safety applications
    • Documentation available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3
    • Hardware integrity up to SIL 2
    • Safety-related certification
  • Functional Safety Features
    • ECC or parity on calculation-critical memories
    • ECC and parity on select internal bus interconnect
    • Built-In Self-Test (BIST) for CPU and on-chip RAM
    • Error Signaling Module (ESM) with error pin
    • Runtime safety diagnostics, voltage, temperature, and clock monitoring, windowed watchdog timers, CRC engine for memory integrity checks
    • Dedicated MCU domain memory, interfaces, and M4F core capable of being isolated from the larger SoC with Freedom From Interference (FFI) features
      • Separate interconnect
      • Firewalls and timeout gaskets
      • Dedicated PLL
      • Dedicated I/O supply
      • Separate reset

SoC architecture:

  • Supports primary boot from UART, I2C, OSPI/QSPI Flash, SPI Flash, parallel NOR Flash, parallel NAND Flash, SD, eMMC, USB, PCIe, and Ethernet interfaces
  • 16-nm FinFET technology
  • 17.2mm × 17.2mm, 0.8-mm pitch, 441-pin BGA package

AM64x is an extension of the Sitara™ Industrial-grade family of heterogeneous Arm® processors. AM64x is built for industrial applications, such as motor drives and Programmable Logic Controllers (PLCs), which require a unique combination of real-time processing and communications with applications processing. AM64x combines two instances of the Sitara device’s gigabit TSN-enabled PRU-ICSSG with up to two Arm® Cortex®-A53 cores, up to four Cortex-R5F MCUs, and a Cortex-M4F MCU.

AM64x is architected to provide real-time performance through the high-performance R5Fs, Tightly-Coupled Memory banks, configurable SRAM partitioning, and dedicated low-latency paths to and from peripherals for rapid data movement in and out of the SoC. This deterministic architecture allows for AM64x to handle the tight control loops found in servo drives while the peripherals like FSI, GPMC, PWMs, sigma delta decimation filters, and absolute encoder interfaces help enable a number of different architectures found in these systems.

The Cortex-A53s provide the powerful computing elements necessary for Linux applications. Linux, and Real-time (RT) Linux, is provided through TI’s Processor SDK Linux which stays updated to the latest Long Term Support (LTS) Linux kernel, bootloader and Yocto file system on an annual basis. AM64x helps bridge the Linux world with the real-time world by enabling isolation between Linux applications and real-time streams through configurable memory partitioning. The Cortex-A53s can be assigned to work strictly out of DDR for Linux, and the internal SRAM can be broken up into various sizes for the Cortex-R5Fs to use together or independently.

The AM64x provides flexible industrial communications capability including full protocol stacks for EtherCAT SubDevice, PROFINET device, EtherNet/IP adapter, and IO-Link Master. The PRU-ICSSG further provides capability for gigabit and TSN based protocols. In addition, the PRU-ICSSG also enables additional interfaces in the SoC including sigma delta decimation filters and absolute encoder interfaces.

Functional safety features can be enabled through the integrated Cortex-M4F along with dedicated peripherals which can all be isolated from the rest of the SoC. AM64x also supports secure boot.

AM64x is an extension of the Sitara™ Industrial-grade family of heterogeneous Arm® processors. AM64x is built for industrial applications, such as motor drives and Programmable Logic Controllers (PLCs), which require a unique combination of real-time processing and communications with applications processing. AM64x combines two instances of the Sitara device’s gigabit TSN-enabled PRU-ICSSG with up to two Arm® Cortex®-A53 cores, up to four Cortex-R5F MCUs, and a Cortex-M4F MCU.

AM64x is architected to provide real-time performance through the high-performance R5Fs, Tightly-Coupled Memory banks, configurable SRAM partitioning, and dedicated low-latency paths to and from peripherals for rapid data movement in and out of the SoC. This deterministic architecture allows for AM64x to handle the tight control loops found in servo drives while the peripherals like FSI, GPMC, PWMs, sigma delta decimation filters, and absolute encoder interfaces help enable a number of different architectures found in these systems.

The Cortex-A53s provide the powerful computing elements necessary for Linux applications. Linux, and Real-time (RT) Linux, is provided through TI’s Processor SDK Linux which stays updated to the latest Long Term Support (LTS) Linux kernel, bootloader and Yocto file system on an annual basis. AM64x helps bridge the Linux world with the real-time world by enabling isolation between Linux applications and real-time streams through configurable memory partitioning. The Cortex-A53s can be assigned to work strictly out of DDR for Linux, and the internal SRAM can be broken up into various sizes for the Cortex-R5Fs to use together or independently.

The AM64x provides flexible industrial communications capability including full protocol stacks for EtherCAT SubDevice, PROFINET device, EtherNet/IP adapter, and IO-Link Master. The PRU-ICSSG further provides capability for gigabit and TSN based protocols. In addition, the PRU-ICSSG also enables additional interfaces in the SoC including sigma delta decimation filters and absolute encoder interfaces.

Functional safety features can be enabled through the integrated Cortex-M4F along with dedicated peripherals which can all be isolated from the rest of the SoC. AM64x also supports secure boot.
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Technical documentation

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Type Title Date
* Data sheet AM64x Sitara™ Processors datasheet (Rev. G) PDF | HTML 21 Apr 2024
* Errata AM64x/AM243x Processor Silicon Revision 1.0, 2.0 (Rev. H) PDF | HTML 21 Dec 2023
* User guide AM64x/AM243x Technical Reference Manual (Rev. H) PDF | HTML 08 Jan 2024
Application note Industrial Communication Protocols Supported on Sitara™ Processors (Rev. E) PDF | HTML 10 May 2024
White paper Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) PDF | HTML 30 Apr 2024
Functional safety information AM64x, AM243x IEC61508 TUV SUD Functional Safety Certificate 25 Mar 2024
Application note Sitara™AM64x /AM243x BenchmarksCortex-R5 Memory Access Latency (Rev. B) PDF | HTML 24 Jan 2024
Application note Using TSN Ethernet Features to Improve Timing in Industrial Ethernet Controllers PDF | HTML 15 Nov 2023
White paper Securing Arm-Based Application Processors (Rev. E) 09 Nov 2023
Application note Sitara Processor Power Distribution Networks: Implementation and Analysis (Rev. G) PDF | HTML 28 Aug 2023
Application note Integration of MbedTLS on SITARA MCU Devices PDF | HTML 03 Aug 2023
Application note Hardware Design Guide for AM6442, AM6422, AM6412 and AM2434 Processors (Rev. A) PDF | HTML 24 Jul 2023
Application note Intra Drive Communication Using 8b-10b Line Code With Programmable Real Time Uni PDF | HTML 24 May 2023
Application note High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 24 Feb 2023
Application note AM6442, AM6422, AM6412 and AM2434 Schematic Design and Review Checklist (Rev. C) PDF | HTML 11 Jan 2023
Application note PRU-ICSS Feature Comparison (Rev. G) PDF | HTML 11 Oct 2022
Application note Powering the AM64x with the TPS65220 or TPS65219 PMIC PDF | HTML 22 Sep 2022
Application note Optimized Trigonometric Functions on TI Arm Cores (Rev. A) PDF | HTML 08 Aug 2022
Application note AM64x/AM243x Extended Power-On Hours PDF | HTML 05 Aug 2022
Product overview Voltage Translation Application Quick Reference PDF | HTML 28 Jun 2022
Application note AM243x/AM64x Single Chip Motor Control Benchmark PDF | HTML 30 Mar 2022
Application note Using LP8733xx and TPS65218xx PMICs to Power AM64x and AM243x Sitara Processors PDF | HTML 16 Feb 2022
More literature Quick Start Guide for Wi-SUN® Wireless MCUs and Transceivers PDF | HTML 14 Jan 2022
Application brief Powering the AM64xx With the LP8733xx PMIC PDF | HTML 15 Jul 2021
Application note AM64x/AM243x DDR Board Design and Layout Guidelines (Rev. A) PDF | HTML 01 Jul 2021
Application note AM64x/AM243x Power Estimation Tool (Rev. A) PDF | HTML 01 Jul 2021
User guide AM64x/AM243x BGA Escape Routing (Rev. A) PDF | HTML 06 Apr 2021
More literature Decentralized servo architecture webinar 01 Mar 2021
Technical article Compact. Precise. Connected. Increase productivity with intelligent edge computing PDF | HTML 01 Feb 2021
More literature From Start to Finish: A Product Development Roadmap for Sitara™ Processors 16 Dec 2020
Application note AM64x SerDes IBIS AMI README PDF | HTML 02 Dec 2020

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