ADS58J89
- 4-Ch, 14-Bit 500MSPS With Digital Signal Processing
- Power Amplifier Linearization (Feedback) Modes
- 14-Bits Every Other Sample at 250MSPS
- Programmable Resolution vs Duty Cycle
- Duty Cycle 3:2 (60% 11-Bit, 40% 9-Bit)
- Duty Cycle 2:3 (40% 12-Bit, 60% 9-Bit)
- Duty Cycle 1:3 (25% 14-Bit, 75% 9-Bit)
- Traffic Receiver Modes
- 14-Bit 250MSPS: Decimate by 2 Filter, High/Low Pass
- 9-Bit SNR-Boost Filter (150-MHz Max Bandwidth)
- 9-to-14-Bit TDD Burst (200-MHz Max Bandwidth)
- Flexible Input Clock Buffer With Divide by 1/2/4
- JESD204B Digital Interface up to 5.0Gbps
- 1 or 2 Lanes per Channel, With Subclass 1
- 64-Pin VQFN Package (9 × 9 mm)
The ADS58J89 is a high-linearity, quad-channel, 14-bit, 250/500-MSPS IF (intermediate frequency) receiver. The four channels contain 500MSPS 14-bit ADCs followed by signal processing for wireless infrastructure systems. The channels can be configured in various modes depending on bandwidth, resolution and sample time requirements. The signal processing block contains selectable modes for decimation filters, SNR Boost filters, resolution versus time and time-division duplex (TDD) burst mode. Designed for high antenna count systems, the 4 channels provides high bandwidth and linearity to multi-channel receivers in a small footprint. The device can be dual function as traffic receiver and power amplifier linearization feedback path in TDD systems.
Key Specifications:
- Power Dissipation: 875 mW/ch
- Input Bandwidth (3dB): 900 MHz
- Aperture Jitter: 98 fs rms
- Channel Isolation: 85 dB
- Performance at ∫in = 170 MHz at 1.25 Vpp,
–1 dBFS- SNR: 65.8 dBFS
- SFDR: 85 dBc HD2,3 95 dBFS non HD2,3
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | ADS58J89 Quad Channel 14-Bit 250/500 MSPS Receiver and Feedback IC datasheet | PDF | HTML | 2014/11/24 |
設計與開發
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SLAC506 — ADS58J89 EVM SPI GUI Installer v1.1
ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
類比工程師的計算機旨在加速類比電路設計工程師定期使用的許多重複計算。此基於 PC 的工具提供圖形介面，列出各種常見計算，從使用回饋電阻器設定運算放大器增益到選擇適當的電路設計元件以穩定類比數位轉換器 (ADC) 驅動緩衝電路。
除了作為獨立工具使用外，此計算機還與類比工程師口袋參考中描述的概念相得益彰。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RGC) | 64 | Ultra Librarian |