產品詳細資料

Sample rate (max) (Msps) 50 Resolution (Bits) 12 Number of input channels 2 Interface type Parallel CMOS Analog input BW (MHz) 270 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2, 3 Power consumption (typ) (mW) 720 Architecture Pipeline SNR (dB) 68 ENOB (Bits) 10.5 SFDR (dB) 72.7 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 50 Resolution (Bits) 12 Number of input channels 2 Interface type Parallel CMOS Analog input BW (MHz) 270 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2, 3 Power consumption (typ) (mW) 720 Architecture Pipeline SNR (dB) 68 ENOB (Bits) 10.5 SFDR (dB) 72.7 Operating temperature range (°C) -40 to 85 Input buffer No
HTQFP (PAP) 64 144 mm² 12 x 12
  • HIGH SNR: 66dB (2Vp-p), 68dB (3Vp-p)
  • LOW POWER: 720mW
  • INTERNAL OR EXTERNAL REFERENCE
  • LOW DLE: 0.6LSB
  • FLEXIBLE INPUT RANGE: 2Vp-p to 3Vp-p
  • TQFP-64 POWER PACKAGE
  • APPLICATIONS
    • COMMUNICATIONS IF PROCESSING
    • COMMUNICATIONS BASESTATIONS
    • TEST EQUIPMENT
    • MEDICAL IMAGING
    • VIDEO DIGITIZING
    • CCD DIGITIZING

  • HIGH SNR: 66dB (2Vp-p), 68dB (3Vp-p)
  • LOW POWER: 720mW
  • INTERNAL OR EXTERNAL REFERENCE
  • LOW DLE: 0.6LSB
  • FLEXIBLE INPUT RANGE: 2Vp-p to 3Vp-p
  • TQFP-64 POWER PACKAGE
  • APPLICATIONS
    • COMMUNICATIONS IF PROCESSING
    • COMMUNICATIONS BASESTATIONS
    • TEST EQUIPMENT
    • MEDICAL IMAGING
    • VIDEO DIGITIZING
    • CCD DIGITIZING

The ADS2807 is a dual, high-speed, high dynamic range, 12-bit pipelined Analog-to-Digital Converter (ADC). This converter includes a high-bandwidth track-and-hold that gives excellent spurious performance up to and beyond the Nyquist rate. The differential nature of this track-and-hold and ADC circuitry minimizes even-order harmonics and gives excellent common-mode noise immunity. The track-and-hold can also be operated single-ended.

The ADS2807 provides for setting the full-scale range of the converter without any external reference circuitry. The internal reference can be disabled allowing low-drive, external references to be used for improved tracking in multichannel systems.

The ADS2807 provides an over-range indicator flag to indicate an input signal that exceeds the full-scale input range of the converter. This flag can be used to reduce the gain of front-end gain control circuitry. There is also an output enable pin to allow for multiplexing and testability on a PC board.

The ADS2807 employs digital error correction techniques to provide excellent differential linearity for demanding imaging applications. The ADS2807 is available in a TQFP-64 power package.

The ADS2807 is a dual, high-speed, high dynamic range, 12-bit pipelined Analog-to-Digital Converter (ADC). This converter includes a high-bandwidth track-and-hold that gives excellent spurious performance up to and beyond the Nyquist rate. The differential nature of this track-and-hold and ADC circuitry minimizes even-order harmonics and gives excellent common-mode noise immunity. The track-and-hold can also be operated single-ended.

The ADS2807 provides for setting the full-scale range of the converter without any external reference circuitry. The internal reference can be disabled allowing low-drive, external references to be used for improved tracking in multichannel systems.

The ADS2807 provides an over-range indicator flag to indicate an input signal that exceeds the full-scale input range of the converter. This flag can be used to reduce the gain of front-end gain control circuitry. There is also an output enable pin to allow for multiplexing and testability on a PC board.

The ADS2807 employs digital error correction techniques to provide excellent differential linearity for demanding imaging applications. The ADS2807 is available in a TQFP-64 power package.

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重要文件 類型 標題 格式選項 日期
* Data sheet ADS2807: Dual, 12-Bit, 50Mhz Sampling, Analog-to-Digital Converter datasheet (Rev. B) 2002年 4月 30日
Application note Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) 2010年 9月 10日
Application note Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio 2009年 4月 28日
Application note CDCE62005 as Clock Solution for High-Speed ADCs 2008年 9月 4日
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 2008年 6月 8日
Application note Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 2008年 6月 2日

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