ADS5263
- Maximum Sample Rate: 100 MSPS
- Programmable Device Resolution
- Quad-Channel, 16-Bit, High-SNR Mode
- Quad-Channel, 14-Bit, Low-Power Mode
- 16-Bit High-SNR Mode
- 1.4 W Total Power at 100 MSPS
- 355 mW / Channel
- 4 Vpp Full-scale Input
- 85-dBFS SNR at fin = 3 MHz, 100 MSPS
- 1.4 W Total Power at 100 MSPS
- 14-Bit Low-Power Mode
- 785 mW Total Power at 100 MSPS
- 195 mW/Channel
- 2-Vpp Full-Scale Input
- 74-dBFS SNR at fin = 10 MHz
- Integrated Clamp (for interfacing to
CCD sensors)
- 785 mW Total Power at 100 MSPS
- Low-Frequency Noise Suppression
- Digital Processing Block
- Programmable FIR Decimation Filters
- Programmable Digital Gain: 0 dB to 12 dB
- 2- or 4-Channel Averaging
- Programmable Mapping Between ADC Input
Channels and LVDS Output Pins–Eases Board
Design - Variety of Test Patterns to Verify Data Capture by
FPGA/Receiver - Serialized LVDS Outputs
- Internal and External References
- 3.3-V Analog Supply
- 1.8-V Digital Supply
- Recovers From 6-dB Overload Within 1 Clock
Cycle - Package:
- 9-mm × 9-mm 64-Pin QFN
- Non-Magnetic Package Option for MRI
Systems
- CMOS Technology
Using CMOS process technology and innovative circuit techniques, the ADS5263 is designed to operate at low power and give very high SNR performance with a 4-Vpp full-scale input. Using a low-noise 16-bit front-end stage followed by a 14-bit ADC, the device gives 85-dBFS SNR up to 10 MHz and better than 80-dBFS SNR up to 30 MHz.
ADS5263 has a 14-bit low power mode, where it operates as a quad-channel 14-bit ADC. The 16-bit front-end stage is powered down and the part consumes almost half the power, compared to the 16-bit mode. The 14-bit mode supports a 2-Vpp full-scale input signal, with typical 74-dBFS SNR. The ADS5263 can be dynamically switched between the two resolution modes. This allows systems to use the same part in a high-resolution, high-power mode or a low-resolution, low-power mode.
The device also has a digital processing block that integrates several commonly used digital functions, such as digital gain (up to 12 dB). It includes a digital filter module that has built-in decimation filters (with low-pass, high-pass and band-pass characteristics). The decimation rate is also programmable (by 2, by 4, or by 8). This makes it very useful for narrow-band applications, where the filters can be used to improve SNR and knock-off harmonics, while at the same time reducing the output data rate.
The device includes an averaging mode where two channels (or even four channels) can be averaged to improve SNR. A very unique feature is the programmable mapper module that allows flexible mapping between the input channels and the LVDS output pins. This helps to greatly reduce the complexity of LVDS output routing and can potentially result in cheaper system boards by reducing the number of PCB layers. Specification of device is over industrial temperature range of 40°C to 85°C.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | ADS5263 Quad Channel 16-Bit, 100-MSPS High-SNR ADC datasheet (Rev. D) | PDF | HTML | 2015年 11月 30日 |
Application note | High Speed ADCs and Amplifiers for Flow Cytometry Applications | 2020年 10月 12日 | ||
Application note | Introduction to Magnetic Resonance Imaging (MRI) | 2017年 9月 14日 | ||
Application note | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 2015年 5月 22日 | ||
EVM User's guide | ADS5263EVM Evaluation Module (Rev. A) | 2015年 3月 5日 | ||
Application note | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 2013年 7月 19日 | ||
Application note | Understanding Serial LVDS Capture in High-Speed ADCs | 2013年 7月 10日 | ||
More literature | TI and Altera Ease Design Process with Compatible Evaluation Tools | 2011年 4月 25日 | ||
More literature | TI and Xilinx Ease Design Process with Compatible Evaluation Tools | 2011年 4月 25日 | ||
Application note | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008年 6月 8日 |
設計與開發
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ADS5263EVM — ADS5263 評估模組
ADS5263 為具有高達 100MSPS 取樣頻率的四通道 16 位元 ADC,在 10MHz 輸入下可提供 84.6dBFS 的訊噪比 (SNR)。ADS5263 評估模組 (EVM) 提供一個可在各種時脈和輸入條件下測試 ADS5263 的靈活環境。此 EVM 可讓客戶設計自己的濾波器、產生有對應元件的 EVM 並驗證 EVM 本身性能。
ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)
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封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
VQFN (RGC) | 64 | Ultra Librarian |
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