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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADS5263

現行

四通道 16 位元 100-MSPS 類比轉數位轉換器 (ADC)

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產品規格表

ADS5263

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 100 Resolution (Bits) 14, 16, 18 Number of input channels 4 Interface type Parallel LVDS Analog input BW (MHz) 70 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 4 Power consumption (typ) (mW) 1350 Architecture Pipeline SNR (dB) 85.5 ENOB (Bits) 12.8 SFDR (dB) 81 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 100 Resolution (Bits) 14, 16, 18 Number of input channels 4 Interface type Parallel LVDS Analog input BW (MHz) 70 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 4 Power consumption (typ) (mW) 1350 Architecture Pipeline SNR (dB) 85.5 ENOB (Bits) 12.8 SFDR (dB) 81 Operating temperature range (°C) -40 to 85 Input buffer No
VQFN (RGC) 64 81 mm² 9 x 9
  • Maximum Sample Rate: 100 MSPS
  • Programmable Device Resolution
    • Quad-Channel, 16-Bit, High-SNR Mode
    • Quad-Channel, 14-Bit, Low-Power Mode
  • 16-Bit High-SNR Mode
    • 1.4 W Total Power at 100 MSPS
      • 355 mW / Channel
    • 4 Vpp Full-scale Input
    • 85-dBFS SNR at fin = 3 MHz, 100 MSPS
  • 14-Bit Low-Power Mode
    • 785 mW Total Power at 100 MSPS
      • 195 mW/Channel
    • 2-Vpp Full-Scale Input
    • 74-dBFS SNR at fin = 10 MHz
    • Integrated Clamp (for interfacing to
      CCD sensors)
  • Low-Frequency Noise Suppression
  • Digital Processing Block
    • Programmable FIR Decimation Filters
    • Programmable Digital Gain: 0 dB to 12 dB
    • 2- or 4-Channel Averaging
  • Programmable Mapping Between ADC Input
    Channels and LVDS Output Pins–Eases Board
    Design
  • Variety of Test Patterns to Verify Data Capture by
    FPGA/Receiver
  • Serialized LVDS Outputs
  • Internal and External References
  • 3.3-V Analog Supply
  • 1.8-V Digital Supply
  • Recovers From 6-dB Overload Within 1 Clock
    Cycle
  • Package:
    • 9-mm × 9-mm 64-Pin QFN
    • Non-Magnetic Package Option for MRI
      Systems
  • CMOS Technology
  • Maximum Sample Rate: 100 MSPS
  • Programmable Device Resolution
    • Quad-Channel, 16-Bit, High-SNR Mode
    • Quad-Channel, 14-Bit, Low-Power Mode
  • 16-Bit High-SNR Mode
    • 1.4 W Total Power at 100 MSPS
      • 355 mW / Channel
    • 4 Vpp Full-scale Input
    • 85-dBFS SNR at fin = 3 MHz, 100 MSPS
  • 14-Bit Low-Power Mode
    • 785 mW Total Power at 100 MSPS
      • 195 mW/Channel
    • 2-Vpp Full-Scale Input
    • 74-dBFS SNR at fin = 10 MHz
    • Integrated Clamp (for interfacing to
      CCD sensors)
  • Low-Frequency Noise Suppression
  • Digital Processing Block
    • Programmable FIR Decimation Filters
    • Programmable Digital Gain: 0 dB to 12 dB
    • 2- or 4-Channel Averaging
  • Programmable Mapping Between ADC Input
    Channels and LVDS Output Pins–Eases Board
    Design
  • Variety of Test Patterns to Verify Data Capture by
    FPGA/Receiver
  • Serialized LVDS Outputs
  • Internal and External References
  • 3.3-V Analog Supply
  • 1.8-V Digital Supply
  • Recovers From 6-dB Overload Within 1 Clock
    Cycle
  • Package:
    • 9-mm × 9-mm 64-Pin QFN
    • Non-Magnetic Package Option for MRI
      Systems
  • CMOS Technology

Using CMOS process technology and innovative circuit techniques, the ADS5263 is designed to operate at low power and give very high SNR performance with a 4-Vpp full-scale input. Using a low-noise 16-bit front-end stage followed by a 14-bit ADC, the device gives 85-dBFS SNR up to 10 MHz and better than 80-dBFS SNR up to 30 MHz.

ADS5263 has a 14-bit low power mode, where it operates as a quad-channel 14-bit ADC. The 16-bit front-end stage is powered down and the part consumes almost half the power, compared to the 16-bit mode. The 14-bit mode supports a 2-Vpp full-scale input signal, with typical 74-dBFS SNR. The ADS5263 can be dynamically switched between the two resolution modes. This allows systems to use the same part in a high-resolution, high-power mode or a low-resolution, low-power mode.

The device also has a digital processing block that integrates several commonly used digital functions, such as digital gain (up to 12 dB). It includes a digital filter module that has built-in decimation filters (with low-pass, high-pass and band-pass characteristics). The decimation rate is also programmable (by 2, by 4, or by 8). This makes it very useful for narrow-band applications, where the filters can be used to improve SNR and knock-off harmonics, while at the same time reducing the output data rate.

The device includes an averaging mode where two channels (or even four channels) can be averaged to improve SNR. A very unique feature is the programmable mapper module that allows flexible mapping between the input channels and the LVDS output pins. This helps to greatly reduce the complexity of LVDS output routing and can potentially result in cheaper system boards by reducing the number of PCB layers. Specification of device is over industrial temperature range of –40°C to 85°C.

Using CMOS process technology and innovative circuit techniques, the ADS5263 is designed to operate at low power and give very high SNR performance with a 4-Vpp full-scale input. Using a low-noise 16-bit front-end stage followed by a 14-bit ADC, the device gives 85-dBFS SNR up to 10 MHz and better than 80-dBFS SNR up to 30 MHz.

ADS5263 has a 14-bit low power mode, where it operates as a quad-channel 14-bit ADC. The 16-bit front-end stage is powered down and the part consumes almost half the power, compared to the 16-bit mode. The 14-bit mode supports a 2-Vpp full-scale input signal, with typical 74-dBFS SNR. The ADS5263 can be dynamically switched between the two resolution modes. This allows systems to use the same part in a high-resolution, high-power mode or a low-resolution, low-power mode.

The device also has a digital processing block that integrates several commonly used digital functions, such as digital gain (up to 12 dB). It includes a digital filter module that has built-in decimation filters (with low-pass, high-pass and band-pass characteristics). The decimation rate is also programmable (by 2, by 4, or by 8). This makes it very useful for narrow-band applications, where the filters can be used to improve SNR and knock-off harmonics, while at the same time reducing the output data rate.

The device includes an averaging mode where two channels (or even four channels) can be averaged to improve SNR. A very unique feature is the programmable mapper module that allows flexible mapping between the input channels and the LVDS output pins. This helps to greatly reduce the complexity of LVDS output routing and can potentially result in cheaper system boards by reducing the number of PCB layers. Specification of device is over industrial temperature range of –40°C to 85°C.
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技術文件

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重要文件 類型 標題 格式選項 日期
* Data sheet ADS5263 Quad Channel 16-Bit, 100-MSPS High-SNR ADC datasheet (Rev. D) PDF | HTML 2015年 11月 30日
Application note High Speed ADCs and Amplifiers for Flow Cytometry Applications 2020年 10月 12日
Application note Introduction to Magnetic Resonance Imaging (MRI) 2017年 9月 14日
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 2015年 5月 22日
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 2013年 7月 19日
Application note Understanding Serial LVDS Capture in High-Speed ADCs 2013年 7月 10日
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 2008年 6月 8日

設計與開發

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開發板

ADS5263EVM — ADS5263 評估模組

ADS5263 為具有高達 100MSPS 取樣頻率的四通道 16 位元 ADC，在 10MHz 輸入下可提供 84.6dBFS 的訊噪比 (SNR)。ADS5263 評估模組 (EVM) 提供一個可在各種時脈和輸入條件下測試 ADS5263 的靈活環境。此 EVM 可讓客戶設計自己的濾波器、產生有對應元件的 EVM 並驗證 EVM 本身性能。

請注意，ADS5263EVM 評估需要 TSW1400EVM (停產)。建議您不要購買 ADS5263EVM，除非您已擁有 TSW1400EVM。

使用指南: PDF
TI.com 無法提供
開發模組 (EVM) 的 GUI

SLAC476 — ADS5263EVM GUI Installer v2.2

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模擬型號

ADS5263 IBIS Model

SLAM080.ZIP (26 KB) - IBIS Model
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計算工具

ANALOG-ENGINEER-CALC — PC software analog engineer's calculator

The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)

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模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI 是有助於評估類比電路功能的設計和模擬環境。這款全功能設計和模擬套件使用 Cadence® 的類比分析引擎。PSpice for TI 包括業界最大的模型庫之一，涵蓋我們的類比和電源產品組合，以及特定類比行為模型，且使用無需支付費用。

PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前，建立完整的終端設備設計和解決方案原型，進而縮短上市時間並降低開發成本。 

在 PSpice for TI 設計與模擬工具中，您可以搜尋 TI (...)
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
VQFN (RGC) 64 Ultra Librarian
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