產品詳細資料

Sample rate (max) (Msps) 500 Resolution (Bits) 12 Number of input channels 1 Interface type DDR LVDS Analog input BW (MHz) 1200 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 1 Power consumption (typ) (mW) 1040 Architecture Pipeline SNR (dB) 60.8 ENOB (Bits) 9.8 SFDR (dB) 80 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 500 Resolution (Bits) 12 Number of input channels 1 Interface type DDR LVDS Analog input BW (MHz) 1200 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 1 Power consumption (typ) (mW) 1040 Architecture Pipeline SNR (dB) 60.8 ENOB (Bits) 9.8 SFDR (dB) 80 Operating temperature range (°C) -40 to 85 Input buffer No
NFBGA (ZAY) 196 144 mm² 12 x 12
  • Single Channel
  • 12-Bit Resolution
  • Maximum Clock Rate: 500 Msps
  • Low Swing Fullscale Input: 1.0 Vpp
  • Analog Input Buffer with High Impedance Input
  • Input Bandwidth (3dB): >1.2GHz
  • Data Output Interface: DDR LVDS
  • 196-Pin BGA Package (12×12mm)
  • Power Dissipation: 1 W
  • Spectral Performance at fIN = 230 MHz IF
    • SNR: 60.6 dBFS
    • SFDR: 80 dBc
  • Spectral Performance at fIN = 700 MHz IF
    • SNR: 59.5 dBFS
    • SFDR: 72 dBc
  • Single Channel
  • 12-Bit Resolution
  • Maximum Clock Rate: 500 Msps
  • Low Swing Fullscale Input: 1.0 Vpp
  • Analog Input Buffer with High Impedance Input
  • Input Bandwidth (3dB): >1.2GHz
  • Data Output Interface: DDR LVDS
  • 196-Pin BGA Package (12×12mm)
  • Power Dissipation: 1 W
  • Spectral Performance at fIN = 230 MHz IF
    • SNR: 60.6 dBFS
    • SFDR: 80 dBc
  • Spectral Performance at fIN = 700 MHz IF
    • SNR: 59.5 dBFS
    • SFDR: 72 dBc

The ADS5403 is a high linearity single channel 12-bit, 500 MSPS analog-to-digital converter (ADC) easing front end filter design for wide bandwidth receivers. The analog input buffer isolates the internal switching of the on-chip track-and-hold from disturbing the signal source as well as providing a high-impedance input. Optionally the output data can be decimated by two. Designed for high SFDR, the ADC has low-noise performance and outstanding spurious-free dynamic range over a large input-frequency range. The device is available in a 196pin BGA package and is specified over the full industrial temperature range (–40°C to 85°C).

The ADS5403 is a high linearity single channel 12-bit, 500 MSPS analog-to-digital converter (ADC) easing front end filter design for wide bandwidth receivers. The analog input buffer isolates the internal switching of the on-chip track-and-hold from disturbing the signal source as well as providing a high-impedance input. Optionally the output data can be decimated by two. Designed for high SFDR, the ADC has low-noise performance and outstanding spurious-free dynamic range over a large input-frequency range. The device is available in a 196pin BGA package and is specified over the full industrial temperature range (–40°C to 85°C).

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重要文件 類型 標題 格式選項 日期
* Data sheet Single Channel 12-Bit 500Msps Receiver and Feedback IC, ADS5403 datasheet (Rev. B) 2014年 1月 8日
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 2015年 5月 22日
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 2013年 7月 19日

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ADS5403EVM — ADS5403 12 位元、500 MSPS 類比轉數位轉換器評估模組

ADS540x 和 ADS54T0x EVM 是一款電路板,能讓設計人員評估德州儀器 (TI) ADS5401/02/03/04/07/09 (單/雙通道 12 位元 500/800/900 MSPS 類比轉數位轉換器),以及 ADS54T01/T04/T02 (單/雙通道 500/750MSPS BTS 回饋和接收器 IC) 性能。ADC 具有平行 DDR LVDS 輸出。EVM 提供一個可在各種時鐘、類比輸入和供電條件下測試 ADS540x 的靈活環境。對於 ADS54T0x EVM,可以使用多種方法為 EVM 提供觸發訊號以啟動突發高解析度輸出。

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NFBGA (ZAY) 196 Ultra Librarian

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