ADS5541
- 14-Bit Resolution
- 105MSPS Sample Rate
- High SNR: 72dBFS at 100MHz fIN
- High SFDR: 86dBc at 100MHz fIN
- 2.3VPP Differential Input Voltage
- Internal Voltage Reference
- 3.3V Single-Supply Voltage
- Analog Power Dissipation: 571mW
- Serial Programming Interface
- TQFP-64 PowerPAD™ Package
- Pin-Compatible With:
- ADS5500 (14-Bit, 125MSPS)
- ADS5542 (14-Bit, 80MSPS)
- ADS5520 (12-Bit, 125MSPS)
- ADS5521 (12-Bit, 105MSPS)
- ADS5522 (12-Bit, 80MSPS)
- Recommended Op Amps:
- OPA695, OPA847, THS3202, THS3201, THS4503, THS4509, THS9001
- APPLICATIONS
- Wireless Communication
- Communication Receivers
- Base Station Infrastructure
- Test and Measurement Instrumentation
- Single and Multichannel Digital Receivers
- Communication Instrumentation
- Radar, Infrared
- Video and Imaging
- Medical Equipment
- Military Equipment
- Wireless Communication
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
The ADS5541 is a high-performance, 14-bit, 105MSPS analog-to-digital converter (ADC). To provide a complete converter solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference. Designed for applications demanding the highest speed and highest dynamic performance in a small space, the ADS5541 has excellent analog power dissipation of 571mW at 3.3V single-supply voltage. This allows an even higher system integration density. The provided internal reference simplifies system design requirements. The parallel CMOS compatible outputs ensure seamless interfacing with common logic.
The ADS5541 is available in a TQFP-64 PowerPAD package over the industrial temperature range.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | 14-Bit, 105MSPS Analog-to-Digital Converter datasheet (Rev. C) | 2007/1/31 | |||
| 應用說明 | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 2015/5/22 | ||||
| 應用說明 | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 2013/7/19 | ||||
| 應用說明 | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 2010/9/10 | ||||
| 應用說明 | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 2009/4/28 | ||||
| 應用說明 | CDCE62005 as Clock Solution for High-Speed ADCs | 2008/9/4 | ||||
| 應用說明 | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008/6/8 | ||||
| 應用說明 | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008/6/2 | ||||
| 使用指南 | ADS5500/5541/5542/5520/5521/5522 14-&12-Bit Single Channel ADC w/LVDT1422 Output | 2006/7/26 | ||||
| 類比設計期刊 | Clocking High-Speed Data Converters | 2005/1/18 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
HSADC-SPI-UTILITY — ADS5400 EVM GUI
ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
類比工程師的計算機旨在加速類比電路設計工程師定期使用的許多重複計算。此基於 PC 的工具提供圖形介面，列出各種常見計算，從使用回饋電阻器設定運算放大器增益到選擇適當的電路設計元件以穩定類比數位轉換器 (ADC) 驅動緩衝電路。
除了作為獨立工具使用外，此計算機還與類比工程師口袋參考中描述的概念相得益彰。
JITTER-SNR-CALC — Jitter and SNR calculator
JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| HTQFP (PAP) | 64 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。