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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADS52J91

現行

具有 LVDS 和 JESD 輸出的 10 位元、12 位元和 14 位元、多通道、低功耗 ADC

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產品規格表

ADS52J91

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 100 Resolution (Bits) 10, 14 Number of input channels 8, 16, 32 Interface type JESD204B, Serial LVDS Analog input BW (MHz) 70 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 656 Architecture SAR SNR (dB) 73.5 ENOB (Bits) 10, 12, 14 SFDR (dB) 91.8 Operating temperature range (°C) 0 to 70 Input buffer No
Sample rate (max) (Msps) 100 Resolution (Bits) 10, 14 Number of input channels 8, 16, 32 Interface type JESD204B, Serial LVDS Analog input BW (MHz) 70 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 656 Architecture SAR SNR (dB) 73.5 ENOB (Bits) 10, 12, 14 SFDR (dB) 91.8 Operating temperature range (°C) 0 to 70 Input buffer No
NFBGA (ZZE) 198 135 mm² (9 mm × 15 mm)
  • 16-Channel ADC configurable to convert 8, 16, or 32 inputs
  • Maximum ADC Conversion Rate:
    • 125 MSPS in 10-bit mode
    • 100 MSPS in 12-bit mode
    • 65 MSPS in 14-bit mode
  • Supplies: 1.2 V, 1.8 V
  • Differential or single-ended input Clock
  • Signal-to-noise ratio (SNR):
    • 61 dBFS in 10-bit mode
    • 69 dBFS in 12-bit mode
    • 73.5 dBFS in 14-Bit Mode
  • Power at 125 MSPS: 48.6 mW/channel
  • 16 ADCs configurable to convert:
    • 8 Inputs with a sampling rate of a 2X ADC conversion rate
    • 16 Inputs with a sampling rate of a 1X ADC conversion rate
    • 32 Inputs with a sampling rate of a 0.5X ADC conversion rate
  • 1 Gbps LVDS interface with 16X, 14X, 12X, and 10X serialization
  • 5 Gbps JESD interface:
    • JESD204B Subclass 0, 1, and 2
    • 2, 4, or 8 Channels per JESD lane
  • Package: NFBGA-198 (9 mm × 15 mm)
  • 16-Channel ADC configurable to convert 8, 16, or 32 inputs
  • Maximum ADC Conversion Rate:
    • 125 MSPS in 10-bit mode
    • 100 MSPS in 12-bit mode
    • 65 MSPS in 14-bit mode
  • Supplies: 1.2 V, 1.8 V
  • Differential or single-ended input Clock
  • Signal-to-noise ratio (SNR):
    • 61 dBFS in 10-bit mode
    • 69 dBFS in 12-bit mode
    • 73.5 dBFS in 14-Bit Mode
  • Power at 125 MSPS: 48.6 mW/channel
  • 16 ADCs configurable to convert:
    • 8 Inputs with a sampling rate of a 2X ADC conversion rate
    • 16 Inputs with a sampling rate of a 1X ADC conversion rate
    • 32 Inputs with a sampling rate of a 0.5X ADC conversion rate
  • 1 Gbps LVDS interface with 16X, 14X, 12X, and 10X serialization
  • 5 Gbps JESD interface:
    • JESD204B Subclass 0, 1, and 2
    • 2, 4, or 8 Channels per JESD lane
  • Package: NFBGA-198 (9 mm × 15 mm)

The ADS52J91 is a low-power, high-performance, 16-channel, analog-to-digital converter (ADC). The conversion rate of each ADC goes up to a maximum of 125 MSPS in 10-bit mode. The maximum conversion rate reduces when the ADC resolution is set to a higher value.

The device can be configured to accept 8, 16, or 32 inputs. In 32-input mode, each ADC alternately samples and converts two different inputs each at an effective sampling rate that is half of the ADC conversion rate. In 8-bit input mode, two ADCs convert the same input in an interleaved manner, resulting in an effective sampling rate that is twice the ADC conversion rate. The ADC is designed to scale its power with the conversion rate.

The ADC outputs are serialized and output through a low-voltage differential signaling (LVDS) interface along with a frame clock and a high-speed bit clock.

The device also has an optional JESD204B interface while operating in the 16-input and 32-input modes. This interface runs up to 5 Gbps

The device is available in a 9-mm × 15-mm, 0.8-mm pitch, NFBGA-198 package

The ADS52J91 is a low-power, high-performance, 16-channel, analog-to-digital converter (ADC). The conversion rate of each ADC goes up to a maximum of 125 MSPS in 10-bit mode. The maximum conversion rate reduces when the ADC resolution is set to a higher value.

The device can be configured to accept 8, 16, or 32 inputs. In 32-input mode, each ADC alternately samples and converts two different inputs each at an effective sampling rate that is half of the ADC conversion rate. In 8-bit input mode, two ADCs convert the same input in an interleaved manner, resulting in an effective sampling rate that is twice the ADC conversion rate. The ADC is designed to scale its power with the conversion rate.

The ADC outputs are serialized and output through a low-voltage differential signaling (LVDS) interface along with a frame clock and a high-speed bit clock.

The device also has an optional JESD204B interface while operating in the 16-input and 32-input modes. This interface runs up to 5 Gbps

The device is available in a 9-mm × 15-mm, 0.8-mm pitch, NFBGA-198 package
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* 資料表 ADS52J91 10-Bit, 12-Bit, 14-Bit, Multichannel, Low-Power, High-Speed ADC With LVDS, JESD Outputs datasheet PDF | HTML 2021/9/15

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計算工具

ANALOG-ENGINEER-CALC — PC software analog engineer's calculator

類比工程師的計算機旨在加速類比電路設計工程師定期使用的許多重複計算。此基於 PC 的工具提供圖形介面，列出各種常見計算，從使用回饋電阻器設定運算放大器增益到選擇適當的電路設計元件以穩定類比數位轉換器 (ADC) 驅動緩衝電路。

除了作為獨立工具使用外，此計算機還與類比工程師口袋參考中描述的概念相得益彰。

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NFBGA (ZZE) 198 Ultra Librarian
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