ADS5413
- 12-Bit Resolution
- 65-MSPS Maximum Sample Rate
- 2-Vpp Differential Input Range
- 3.3-V Single Supply Operation
- 1.8-V to 3.3-V Output Supply
- 400-mW Total Power Dissipation
- Two’s Complement Output Format
- On-Chip S/H and Duty Cycle Adjust Circuit
- Internal or External Reference
- 48-Pin TQFP Package With PowerPad
(7 mm x 7 mm body size) - 64.5-dBFS SNR and 72-dBc SFDR at 65 MSPS and 190-MHz Input
- Power-Down Mode
- Single-Ended or Differential Clock
- 1-GHz -3-dB Input Bandwidth
- APPLICATIONS
- High IF Sampling Receivers
- Medical Imaging
- Portable Instrumentation
CommsADC is a trademark of Texas Instruments.
The ADS5413 is a low power, 12-bit, 65-MSPS, CMOS pipeline analog-to-digital converter (ADC) that operates from a single 3.3-V supply, while offering the choice of digital output levels from 1.8 V to 3.3 V. The low noise, high linearity, and low clock jitter makes the ADC well suited for high-input frequency sampling applications. On-chip duty cycle adjust circuit allows the use of a non-50% duty cycle. This can be bypassed for applications requiring low jitter or asynchronous sampling. The device can also be clocked with single ended or differential clock, without change in performance. The internal reference can be bypassed to use an external reference to suit the accuracy and low drift requirements of the application.
The device is specified over full temperature range (–40°C to +85°C).
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | ADS5413: 12-bit, 65 MSPS CommsADC Analog-to-Digital Converter datasheet | 2003/12/16 | |||
| 應用說明 | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 2015/5/22 | ||||
| 應用說明 | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 2013/7/19 | ||||
| 應用說明 | High-Speed, Analog-to-Digital Converter Basics | 2012/1/11 | ||||
| 應用說明 | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 2010/9/10 | ||||
| 應用說明 | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 2009/4/28 | ||||
| 應用說明 | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008/6/8 | ||||
| 應用說明 | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008/6/2 | ||||
| 應用說明 | Standard Procedure Direct Measurement Sub-picosecond RMS Jitter High-Speed ADC | 2004/6/30 | ||||
| 應用說明 | How to Calculate the Period Jitter from the SSCR for High-Speed ADCs | 2003/12/17 |
設計與開發
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ADC-HARMONIC-CALC — ADC Frequency Calculator Download
The ADC Harmonic Calculation tool is an excel based calculator for determining the location in frequency space of high order harmonics following Nyquist aliasing in an analog to digital converter.
Given an ADC sample rate and the span of a signal of interest the calcultor will determine if the 2nd (...)
ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
類比工程師的計算機旨在加速類比電路設計工程師定期使用的許多重複計算。此基於 PC 的工具提供圖形介面，列出各種常見計算，從使用回饋電阻器設定運算放大器增益到選擇適當的電路設計元件以穩定類比數位轉換器 (ADC) 驅動緩衝電路。
除了作為獨立工具使用外，此計算機還與類比工程師口袋參考中描述的概念相得益彰。
JITTER-SNR-CALC — Jitter and SNR calculator
JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.
SBAC119 — TIGAR (Texas Instruments Graphical Evaluation of ADC Response Tool)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| HTQFP (PHP) | 48 | Ultra Librarian |
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