ADS5292
- Maximum Sample Rate: 80 MSPS/12-Bit
- High Signal-to-Noise Ratio
- 70-dBFS SNR at 5 MHz/80 MSPS
- 71.5-dBFS SNR at 5 MHz/80 MSPS and Decimation Filter = 2
- 85-dBc SFDR at 5 MHz/80 MSPS
- Low Power Consumption
- 48 mW/CH at 50 MSPS
- 54 mW/CH at 65 MSPS
- 66 mW/CH at 80 MSPS (2 LVDS Wire Per Channel)
- Digital Processing Block
- Programmable FIR Decimation Filter and Oversampling to Minimize
Harmonic Interference - Programmable IIR High Pass Filter to Minimize DC Offset
- Programmable Digital Gain: 0 dB to 12 dB
- 2- or 4-=Channel Averaging
- Programmable FIR Decimation Filter and Oversampling to Minimize
- Flexible Serialized LVDS Outputs:
- One or Two wires of LVDS Output Lines per Channel Depending on ADC
Sampling Rate - Programmable Mapping Between ADC Input Channels and LVDS Output
Pins-Eases Board Design - Variety of Test Patterns to Verify Data Capture by
FPGA/Receiver
- One or Two wires of LVDS Output Lines per Channel Depending on ADC
- Internal and External References
- 1.8V Operation for Low Power Consumption
- Low-Frequency Noise Suppression
- Recovery From 6-dB Overload within 1 Clock Cycle
- Package: 12-mm × 12-mm 80-Pin QFP
Using CMOS process technology and innovative circuit techniques, the ADS5292 is a low power 80MSPS 8-Channel ADC. Low power consumption, high SNR, low SFDR, and consistent overload recovery allow users to design high performance systems.
The ADS5292 has a digital processing block that integrates several commonly used digital functions for improving system performance. It includes a digital filter module that has built-in decimation filters (with low-pass, high-pass and band-pass characteristics). The decimation rate is also programmable (by 2, by 4, or by 8). This makes it useful for narrow-band applications, where the filters can be used conveniently to improve SNR and knock-off harmonics, while at the same time reducing the output data rate. The device includes an averaging mode where two channels (or even four channels) can be averaged to improve SNR.
Serial LVDS outputs reduce the number of interface lines and enable the highest system integration. The digital data from each channel ADC can be output over one or two wires of LVDS output lines depending on the ADC sampling rate. This 2-wire interface helps keep the serial data rate low, allowing low cost FPGA based receivers to be used even at high sample rate. A unique feature is the programmable mapping module that allows flexible mapping between the input channels and the LVDS output pins. This helps greatly reduce the complexity of LVDS output routing and can potentially result in cheaper system boards by reducing the number of PCB layers.
The device integrates an internal reference trimmed to accurately match across devices. Best performance is expected to be achieved through the internal reference mode. The device can be driven with external references as well.
The device is available in a 12 mm × 12 mm 80-pin QFP. It is specified over a –40°C to 85°C operating temperature range. ADS5292 is completely pin-to-pin and register compatible to ADS5294.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | Octal Channel 12-Bit, 80 MSPS and Low-Power ADC datasheet (Rev. B) | 2012年 7月 25日 | |
Application note | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 2015年 5月 22日 | ||
EVM User's guide | ADS5292 EVM (Rev. A) | 2015年 3月 5日 | ||
Application note | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 2013年 7月 19日 | ||
Application note | Understanding Serial LVDS Capture in High-Speed ADCs | 2013年 7月 10日 |
設計與開發
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ADS5292EVM — ADS5292 評估模組
ADS5292 評估模組 (EVM) 提供一個可在各種時脈和輸入條件下測試 ADS5292 的靈活環境。此 EVM 可讓客戶設計自己的濾波器、產生有對應元件的 EVM 並驗證 EVM 本身性能。
SBAC120 — TIGAR Support Files
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高速 ADC (≥10 MSPS)
RF 接收器
硬體開發
開發板
ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)
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精密度運算放大器 (Vos<1mV)
一般用途運算放大器
音訊運算放大器
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高速運算放大器 (GBW ≥ 50 MHz)
功率運算放大器
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SBAC119 — TIGAR (Texas Instruments Graphical Evaluation of ADC Response Tool)
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RF 接收器
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
HTQFP (PFP) | 80 | Ultra Librarian |
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- MTBF/FIT 估算值
- 材料內容
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- 進行中持續性的可靠性監測
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