Using CMOS process technology and innovative circuit techniques, the ADS5263 is designed to operate at low power and give very high SNR performance with a 4-Vpp full-scale input. Using a low-noise 16-bit front-end stage followed by a 14-bit ADC, the device gives 85-dBFS SNR up to 10 MHz and better than 80-dBFS SNR up to 30 MHz.
ADS5263 has a 14-bit low power mode, where it operates as a quad-channel 14-bit ADC. The 16-bit front-end stage is powered down and the part consumes almost half the power, compared to the 16-bit mode. The 14-bit mode supports a 2-Vpp full-scale input signal, with typical 74-dBFS SNR. The ADS5263 can be dynamically switched between the two resolution modes. This allows systems to use the same part in a high-resolution, high-power mode or a low-resolution, low-power mode.
The device also has a digital processing block that integrates several commonly used digital functions, such as digital gain (up to 12 dB). It includes a digital filter module that has built-in decimation filters (with low-pass, high-pass and band-pass characteristics). The decimation rate is also programmable (by 2, by 4, or by 8). This makes it very useful for narrow-band applications, where the filters can be used to improve SNR and knock-off harmonics, while at the same time reducing the output data rate.
The device includes an averaging mode where two channels (or even four channels) can be averaged to improve SNR. A very unique feature is the programmable mapper module that allows flexible mapping between the input channels and the LVDS output pins. This helps to greatly reduce the complexity of LVDS output routing and can potentially result in cheaper system boards by reducing the number of PCB layers. Specification of device is over industrial temperature range of –40°C to 85°C.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | ADS5263 Quad Channel 16-Bit, 100-MSPS High-SNR ADC datasheet (Rev. D) | PDF | HTML | 30 Nov 2015 |
| Application note | High Speed ADCs and Amplifiers for Flow Cytometry Applications | 12 Oct 2020 | ||
| Application note | Introduction to Magnetic Resonance Imaging (MRI) | 14 Sep 2017 | ||
| Application note | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 22 May 2015 | ||
| EVM User's guide | ADS5263EVM Evaluation Module (Rev. A) | 05 Mar 2015 | ||
| Application note | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 19 Jul 2013 | ||
| Application note | Understanding Serial LVDS Capture in High-Speed ADCs | 10 Jul 2013 | ||
| More literature | TI and Altera Ease Design Process with Compatible Evaluation Tools | 25 Apr 2011 | ||
| More literature | TI and Xilinx Ease Design Process with Compatible Evaluation Tools | 25 Apr 2011 | ||
| Application note | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 08 Jun 2008 |
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Analog Engineer's Calc Installer
Software Manifest
General calculator tool for analog design support.