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|*||Data sheet||Dual, 10-Bit, 65MSPS, +3.3V Analog-to-Digital Converter datasheet (Rev. A)||16 Oct 2007|
|Application note||Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)||22 May 2015|
|Application note||Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)||19 Jul 2013|
|Application note||Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)||10 Sep 2010|
|Application note||Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio||28 Apr 2009|
|Application note||CDCE62005 as Clock Solution for High-Speed ADCs||04 Sep 2008|
|Application note||CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters||08 Jun 2008|
|Application note||Phase Noise Performance and Jitter Cleaning Ability of CDCE72010||02 Jun 2008|
|EVM User's guide||ADS5231/32/37 EVM (Rev. B)||14 Nov 2007|
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