Ultra-low power, 50MHz rail-to-rail out, negative rail in, voltage-feedback op amp
Product details
Parameters
Package | Pins | Size
Features
- Ultra-low power:
- Supply voltage: 2.7 V to 5.4 V
- Quiescent current (IQ): 170 µA/ch (typical)
- Bandwidth: 50 MHz (G = 1 V/V)
- Slew rate: 26 V/µs
- Settling time (0.1%): 88 ns (2-VSTEP)
- HD2, HD3: –131 dBc, –146 dBc at 10 kHz (2 VPP)
- Input voltage noise: 12 nV/√Hz (f = 10 kHz)
- Input offset voltage: 350 µV (±1.9 mV max)
- Negative rail input, rail-to-rail output (RRO)
- Input voltage range: –0.2 V to 3.9 V
(5-V supply)
- Input voltage range: –0.2 V to 3.9 V
- Operating temperature range:
–40°C to +125°C
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Description
The OPA2834 is a dual-channel, ultra-low-power, rail-to-rail output, negative-rail input, voltage-feedback (VFB) operational amplifier designed to operate over a power-supply range of 2.7 V to 5.4 V with a single supply, or ±1.35 V to ±2.7 V with a dual supply. Consuming only 170 µA per channel and with a unity-gain bandwidth of 50 MHz, this amplifier sets an industry-leading performance-to-power ratio for rail-to-rail amplifiers.
For battery-powered and portable applications where low power consumption is of key importance, the OPA2834 offers an excellent bandwidth to IQ ratio. OPA2834 offers very low distortion making it very suitable for data acquisition systems and microphone pre-amplifier.
See the Device Comparison Table for a selection of low-power, low-noise, 5-V amplifiers from Texas Instruments with a gain-bandwidth product from 20 MHz to 300 MHz.
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | OPA2834 50-MHz, 170-µA, Negative-Rail In, Rail-to-Rail Out, Voltage-Feedback Amplifier datasheet (Rev. A) | Jul. 12, 2019 |
Technical article | How to reduce distortion in high-voltage, high-frequency signal generation for AWGs | Oct. 30, 2018 | |
Technical article | What are the advantages of using JFET-input amplifiers in high-speed applications? | Jun. 19, 2018 | |
Technical article | Unique active mux capability combines buffer and switch into one solution | Oct. 10, 2017 | |
Technical article | How to minimize filter loss when you drive an ADC | Oct. 20, 2016 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
For more information on these types of op amps, as (...)
Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
Features
- Expedites circuit design with analog-to-digital converters (ADCs) and digital-to-analog converters (DACs)
- Noise calculations
- Common unit translation
- Solves common amplifier circuit design problems
- Gain selections using standard resistors
- Filter configurations
- Total noise for common amplifier configurations
- (...)
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CAD/CAE symbols
Package | Pins | Download |
---|---|---|
VSSOP (DGK) | 8 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Support & training
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