Dual-Channel, 14-Bit, 65-MSPS Analog-to-Digital Converter (ADC)


Product details


Sample rate (Max) (MSPS) 65 Resolution (Bits) 14 Number of input channels 2 Interface type Parallel CMOS Analog input BW (MHz) 750 Features High Performance Rating Catalog Input range (Vp-p) 2.3 Power consumption (Typ) (mW) 725 Architecture Pipeline SNR (dB) 74.4 ENOB (Bits) 11.9 SFDR (dB) 85 Operating temperature range (C) -40 to 85 Input buffer No open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

HTQFP (PFP) 80 196 mm² 14 x 14 open-in-new Find other High-speed ADCs (>10MSPS)


  • Dual ADC
  • 14 Bit Resolution
  • 65 MSPS Sample Rate
  • High SNR = 74 dBFs at 70 MHz fIN
  • High SFDR = 84 dBc at 70 MHz fIN
  • 2.3 VPP Differential Input Voltage
  • Internal / External Voltage Reference
  • 3.3 V Single-Supply Voltage
  • Analog Power Dissipation = 0.72 W
  • Output Supply Power Dissipation = 0.17 W
  • 80 Lead PowerPad™ TQFP Package
  • Two’s Complement Output Format
    • Communication Receivers
    • Base Station Infrastructure
    • Test and Measurement Instrumentation

PowerPAD and CommsADC are trademarks of Texas Instruments.

open-in-new Find other High-speed ADCs (>10MSPS)


The ADS5553 is a high-performance, dual channel, 14 bit, 65 MSPS analog-to-digital converter (ADC). To provide a complete solution, each channel includes a high-bandwidth linear sample-and-hold stage (S& H) and an internal reference. Designed for applications demanding high dynamic performance in a small space, the ADS5553 has excellent power consumption of 0.9 W at 3.3 V single-supply voltage. This allows an even higher system integration density. The provided internal reference simplifies system design requirements, yet an external reference can be used optionally to suit the accuracy and low drift requirements of the application. The outputs are parallel CMOS compatible.

The ADS5553 is available in a 80 lead TQFP PowerPAD package and is specified over the full temperature range of -40°C to 85°C.

open-in-new Find other High-speed ADCs (>10MSPS)

Technical documentation

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Type Title Date
* Datasheet Dual 14 Bit, 65 MSPS ADC datasheet Feb. 21, 2005
Technical article Keys to quick success using high-speed data converters Oct. 13, 2020
Technical article How to achieve fast frequency hopping Mar. 03, 2019
Technical article RF sampling: Learning more about latency Feb. 09, 2017
Technical article Why phase noise matters in RF sampling converters Nov. 28, 2016
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) May 22, 2015
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) Jul. 19, 2013
Application note Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) Sep. 10, 2010
Application note Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio Apr. 28, 2009
Application note CDCE62005 as Clock Solution for High-Speed ADCs Sep. 04, 2008
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters Jun. 08, 2008
Application note Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 Jun. 02, 2008
User guide ADS5553 EVM Mar. 01, 2005
Application note Clocking High-Speed Data Converters Jan. 18, 2005

Design & development

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Software development


Design tools & simulation

SBAC028C.ZIP (343 KB) - IBIS Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
Jitter and SNR Calculator for ADCs
JITTER-SNR-CALC JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.

CAD/CAE symbols

Package Pins Download
HTQFP (PFP) 80 View options

Ordering & quality

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  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

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