Eight-Channel, 14-Bit, 80-MSPS Analog-to-Digital Converter (ADC)


Product details


Sample rate (Max) (MSPS) 80 Resolution (Bits) 12, 14 Number of input channels 8 Interface type Serial LVDS Analog input BW (MHz) 550 Features Low Power Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 464 Architecture Pipeline SNR (dB) 78.2 ENOB (Bits) 12.2 SFDR (dB) 84 Operating temperature range (C) -40 to 85 Input buffer No open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

HTQFP (PFP) 80 196 mm² 14 x 14 open-in-new Find other High-speed ADCs (>10MSPS)


  • Maximum Sample Rate: 80 MSPS/14-Bit
  • High Signal-to-Noise Ratio
    • 75.5-dBFS SNR at 5 MHz / 80 MSPS
    • 78.2-dBFS SNR at 5 MHz / 80 MSPS and Decimation Filter Enabled
    • 84-dBc SFDR at 5 MHz / 80 MSPS
  • Low Power Consumption
    • 58 mW/CH at 50 MSPS
    • 77 mW/CH at 80 MSPS (2-LVDS Wire Per Channel)
  • Digital Processing Block
    • Programmable FIR Decimation Filter and Oversampling to Minimize Harmonic Interference
    • Programmable IIR High-Pass Filter to Minimize DC Offset
    • Programmable Digital Gain: 0 dB to 12 dB
    • 2-Channel or 4-Channel Averaging
  • Flexible Serialized LVDS Outputs:
    • One or Two Wires of LVDS Output Lines Per Channel Depending on ADC Sampling Rate
    • Programmable Mapping Between ADC Input Channels and LVDS Output Pins-Eases Board Design
    • Variety of Test Patterns to Verify Data Capture by FPGA/Receiver
  • Internal and External References
  • 1.8-V Operation for Low Power Consumption
  • Low-Frequency Noise Suppression
  • Recovery From 6-dB Overload Within 1 Clock Cycle
  • Package: 12-mm × 12-mm 80-Pin QFP
open-in-new Find other High-speed ADCs (>10MSPS)


The ADS5294 is a low-power 80-MSPS 8-Channel ADC that uses CMOS process technology and innovative circuit techniques. Low power consumption, high SNR, low SFDR, and consistent overload recovery allow users to design high-performance systems.

The digital processing block of the ADS5294 integrates several commonly used digital functions for improving system performance. The device includes a digital filter module that has built-in decimation filters (with lowpass, highpass and bandpass characteristics). The decimation rate is also programmable (by 2, by 4, or by 8). This rate is useful for narrow-band applications, where the filters are used to conveniently improve SNR and knock-off harmonics, while at the same time reducing the output data rate. The device includes an averaging mode where two channels (or even four channels) are averaged to improve SNR.

Serial LVDS outputs reduce the number of interface lines and enable the highest system integration. The digital data from each channel ADC is output over one or two wires of LVDS output lines depending on the ADC sampling rate. This 2-wire interface maintains a low serial-data rate, allowing low-cost FPGA-based receivers to be used even at a high sample rate. The ADC resolution is programmed to 12-bit or 14-bit through registers. A unique feature is the programmable-mapping module that allows flexible mapping between the input channels and the LVDS output pins. This module greatly reduces the complexity of LVDS-output routing, and by reducing the number of PCB layers, potentially results in cheaper system boards.

The device integrates an internal reference trimmed to accurately match across devices. Internal reference mode achieves the best performance. External references can also drive the device.

The device is available in a 12-mm × 12-mm 80-pin QFP package. The device is specified over a –40°C to 85°C operating temperature range. ADS5294 is completely pin-to-pin and register compatible to ADS5292.

open-in-new Find other High-speed ADCs (>10MSPS)

Technical documentation

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Type Title Date
* Data sheet Octal-Channel 14-Bit 80-MSPS High-SNR and Low-Power ADC datasheet (Rev. E) Apr. 23, 2018
Technical article Keys to quick success using high-speed data converters Oct. 13, 2020
Application note High Speed ADCs and Amplifiers for Flow Cytometry Applications Oct. 12, 2020
Technical article How to achieve fast frequency hopping Mar. 03, 2019
Technical article RF sampling: Learning more about latency Feb. 09, 2017
Technical article Why phase noise matters in RF sampling converters Nov. 28, 2016
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) May 22, 2015
User guide ADS5294, 8-Channel ADC Evaluation Module (Rev. A) Mar. 05, 2015
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) Jul. 19, 2013
Application note Understanding Serial LVDS Capture in High-Speed ADCs Jul. 10, 2013

Design & development

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Hardware development

document-generic User guide

ADS5294EVM provides a flexible environment for testing the ADS5294 under a variety of clock and input conditions. This EVM allows customers to design their own filters, populate the EVM with the corresponding components and verify the performance on the EVM itself.

In the event the user does not (...)

  • Flexible input path
  • Configurable input clock
  • Adaptable to customer own band-pass filter
  • Can directly connect to TSW1400EVM to get parallel CMOS data output
  • Provides extensive software support for control and measurement
  • Software development

    SLAC509.ZIP (114662 KB)

    Design tools & simulation

    SLAM122.ZIP (14 KB) - IBIS Model
    PSpice® for TI design and simulation tool
    PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
    • Leverages Cadence PSpice Technology
    • Preinstalled library with a suite of digital models to enable worst-case timing analysis
    • Dynamic updates ensure you have access to most current device models
    • Optimized for simulation speed without loss of accuracy
    • Supports simultaneous analysis of multiple products
    • (...)

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