Product details

Sample rate (Max) (MSPS) 200 Resolution (Bits) 12 Number of input channels 1 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 800 Features Low Power Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 212 Architecture Pipeline SNR (dB) 70 ENOB (Bits) 11.2 SFDR (dB) 87 Operating temperature range (C) -40 to 85 Input buffer No
Sample rate (Max) (MSPS) 200 Resolution (Bits) 12 Number of input channels 1 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 800 Features Low Power Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 212 Architecture Pipeline SNR (dB) 70 ENOB (Bits) 11.2 SFDR (dB) 87 Operating temperature range (C) -40 to 85 Input buffer No
VQFN (RGZ) 48 49 mm² 7 x 7
  • Maximum Sample Rate: 200 MSPS
  • Ultralow Power with 1.8-V Single Supply:
    • 230-mW Total Power at 200 MSPS
  • High Dynamic Performance:
    • SNR: 69 dBFS at 170 MHz
    • SFDR: 85 dBc at 170 MHz
  • Dynamic Power Scaling With Sample Rate
  • Output Interface:
    • Double Data Rate (DDR) LVDS with
      Programmable Swing and Strength
      • Standard Swing: 350 mV
      • Low Swing: 200 mV
      • Default Strength: 100-Ω Termination
      • 2× Strength: 50-Ω Termination
    • 1.8-V Parallel CMOS Interface Also Supported
  • Programmable Gain up to 6 dB for SNR and

    SFDR Trade-Off
  • DC Offset Correction
  • Supports Low Input Clock Amplitude Down to 200
    mVPP
  • Package: 7.00 mm × 7.00 mm VQFN-48
  • Maximum Sample Rate: 200 MSPS
  • Ultralow Power with 1.8-V Single Supply:
    • 230-mW Total Power at 200 MSPS
  • High Dynamic Performance:
    • SNR: 69 dBFS at 170 MHz
    • SFDR: 85 dBc at 170 MHz
  • Dynamic Power Scaling With Sample Rate
  • Output Interface:
    • Double Data Rate (DDR) LVDS with
      Programmable Swing and Strength
      • Standard Swing: 350 mV
      • Low Swing: 200 mV
      • Default Strength: 100-Ω Termination
      • 2× Strength: 50-Ω Termination
    • 1.8-V Parallel CMOS Interface Also Supported
  • Programmable Gain up to 6 dB for SNR and

    SFDR Trade-Off
  • DC Offset Correction
  • Supports Low Input Clock Amplitude Down to 200
    mVPP
  • Package: 7.00 mm × 7.00 mm VQFN-48

The ADS4128 is a 12-bit analog-to-digital converter (ADC) with sampling rates up to 200 MSPS. This device uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8-V supply. The device is well-suited for multi-carrier, wide-bandwidth communications applications.

The ADS4128 has fine-gain options that can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. It includes a dc offset correction loop that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance.

The ADS4128 is available in a compact VQFN-48 package and is specified over the industrial temperature range (–40°C to 85°C).

The ADS4128 is a 12-bit analog-to-digital converter (ADC) with sampling rates up to 200 MSPS. This device uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8-V supply. The device is well-suited for multi-carrier, wide-bandwidth communications applications.

The ADS4128 has fine-gain options that can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. It includes a dc offset correction loop that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance.

The ADS4128 is available in a compact VQFN-48 package and is specified over the industrial temperature range (–40°C to 85°C).

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Technical documentation

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Type Title Date
* Data sheet ADS4128 12-Bit, 200-MSPS, Ultralow-Power ADC datasheet (Rev. A) 04 Apr 2016
Technical article How smart AFEs offer an integrated analog solution for thermoelectric cooling control 04 Jan 2022
Technical article Keys to quick success using high-speed data converters 13 Oct 2020
Technical article How to achieve fast frequency hopping 03 Mar 2019
Technical article RF sampling: Learning more about latency 09 Feb 2017
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 22 May 2015
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 19 Jul 2013
User guide Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) 10 Jul 2012
User guide ADS41xx/58B18EVM User's Guide.. (Rev. C) 15 May 2012
More literature TI and Altera Ease Design Process with Compatible Evaluation Tools 25 Apr 2011
More literature TI and Xilinx Ease Design Process with Compatible Evaluation Tools 25 Apr 2011

Design & development

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Evaluation board

ADS4128EVM — ADS4128 12-Bit, 200-MSPS Analog-to-Digital Converter Evaluation Module

The ADS4128EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' ADS4128 device, an extremely low power 12-bit 200 MSPS analog to digital converter. The ADC features a configurable parallel DDR LVDS or CMOS outputs. The EVM provides a flexible environment to (...)

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Evaluation board

TSW1405EVM — Data converter data capture evaluation module with 8 LVDS lanes up to 1.0 Gbps

The TSW1405EVM is a low cost data capture circuit board used to evaluate some of Texas Instruments’ (TI) most popular high speed analog-to-digital converters (ADC).

 

The TSW1405EVM supports a high speed LVDS bus capable of providing 16-bit samples at 1.0 GSPS. The platform supports a 64k sample (...)

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Simulation model

ADS4128 IBIS Model

SBAM161.ZIP (164 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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