Product details

Sample rate (Max) (MSPS) 100 Resolution (Bits) 14, 16, 18 Number of input channels 4 Interface type Parallel LVDS Analog input BW (MHz) 70 Features High Performance Rating Catalog Input range (Vp-p) 4 Power consumption (Typ) (mW) 1350 Architecture Pipeline SNR (dB) 85.5 ENOB (Bits) 12.8 SFDR (dB) 81 Operating temperature range (C) -40 to 85 Input buffer No
Sample rate (Max) (MSPS) 100 Resolution (Bits) 14, 16, 18 Number of input channels 4 Interface type Parallel LVDS Analog input BW (MHz) 70 Features High Performance Rating Catalog Input range (Vp-p) 4 Power consumption (Typ) (mW) 1350 Architecture Pipeline SNR (dB) 85.5 ENOB (Bits) 12.8 SFDR (dB) 81 Operating temperature range (C) -40 to 85 Input buffer No
VQFN (RGC) 64 81 mm² 9 x 9
  • Maximum Sample Rate: 100 MSPS
  • Programmable Device Resolution
    • Quad-Channel, 16-Bit, High-SNR Mode
    • Quad-Channel, 14-Bit, Low-Power Mode
  • 16-Bit High-SNR Mode
    • 1.4 W Total Power at 100 MSPS
      • 355 mW / Channel
    • 4 Vpp Full-scale Input
    • 85-dBFS SNR at fin = 3 MHz, 100 MSPS
  • 14-Bit Low-Power Mode
    • 785 mW Total Power at 100 MSPS
      • 195 mW/Channel
    • 2-Vpp Full-Scale Input
    • 74-dBFS SNR at fin = 10 MHz
    • Integrated Clamp (for interfacing to
      CCD sensors)
  • Low-Frequency Noise Suppression
  • Digital Processing Block
    • Programmable FIR Decimation Filters
    • Programmable Digital Gain: 0 dB to 12 dB
    • 2- or 4-Channel Averaging
  • Programmable Mapping Between ADC Input
    Channels and LVDS Output Pins–Eases Board
    Design
  • Variety of Test Patterns to Verify Data Capture by
    FPGA/Receiver
  • Serialized LVDS Outputs
  • Internal and External References
  • 3.3-V Analog Supply
  • 1.8-V Digital Supply
  • Recovers From 6-dB Overload Within 1 Clock
    Cycle
  • Package:
    • 9-mm × 9-mm 64-Pin QFN
    • Non-Magnetic Package Option for MRI
      Systems
  • CMOS Technology
  • Maximum Sample Rate: 100 MSPS
  • Programmable Device Resolution
    • Quad-Channel, 16-Bit, High-SNR Mode
    • Quad-Channel, 14-Bit, Low-Power Mode
  • 16-Bit High-SNR Mode
    • 1.4 W Total Power at 100 MSPS
      • 355 mW / Channel
    • 4 Vpp Full-scale Input
    • 85-dBFS SNR at fin = 3 MHz, 100 MSPS
  • 14-Bit Low-Power Mode
    • 785 mW Total Power at 100 MSPS
      • 195 mW/Channel
    • 2-Vpp Full-Scale Input
    • 74-dBFS SNR at fin = 10 MHz
    • Integrated Clamp (for interfacing to
      CCD sensors)
  • Low-Frequency Noise Suppression
  • Digital Processing Block
    • Programmable FIR Decimation Filters
    • Programmable Digital Gain: 0 dB to 12 dB
    • 2- or 4-Channel Averaging
  • Programmable Mapping Between ADC Input
    Channels and LVDS Output Pins–Eases Board
    Design
  • Variety of Test Patterns to Verify Data Capture by
    FPGA/Receiver
  • Serialized LVDS Outputs
  • Internal and External References
  • 3.3-V Analog Supply
  • 1.8-V Digital Supply
  • Recovers From 6-dB Overload Within 1 Clock
    Cycle
  • Package:
    • 9-mm × 9-mm 64-Pin QFN
    • Non-Magnetic Package Option for MRI
      Systems
  • CMOS Technology

Using CMOS process technology and innovative circuit techniques, the ADS5263 is designed to operate at low power and give very high SNR performance with a 4-Vpp full-scale input. Using a low-noise 16-bit front-end stage followed by a 14-bit ADC, the device gives 85-dBFS SNR up to 10 MHz and better than 80-dBFS SNR up to 30 MHz.

ADS5263 has a 14-bit low power mode, where it operates as a quad-channel 14-bit ADC. The 16-bit front-end stage is powered down and the part consumes almost half the power, compared to the 16-bit mode. The 14-bit mode supports a 2-Vpp full-scale input signal, with typical 74-dBFS SNR. The ADS5263 can be dynamically switched between the two resolution modes. This allows systems to use the same part in a high-resolution, high-power mode or a low-resolution, low-power mode.

The device also has a digital processing block that integrates several commonly used digital functions, such as digital gain (up to 12 dB). It includes a digital filter module that has built-in decimation filters (with low-pass, high-pass and band-pass characteristics). The decimation rate is also programmable (by 2, by 4, or by 8). This makes it very useful for narrow-band applications, where the filters can be used to improve SNR and knock-off harmonics, while at the same time reducing the output data rate.

The device includes an averaging mode where two channels (or even four channels) can be averaged to improve SNR. A very unique feature is the programmable mapper module that allows flexible mapping between the input channels and the LVDS output pins. This helps to greatly reduce the complexity of LVDS output routing and can potentially result in cheaper system boards by reducing the number of PCB layers. Specification of device is over industrial temperature range of –40°C to 85°C.

Using CMOS process technology and innovative circuit techniques, the ADS5263 is designed to operate at low power and give very high SNR performance with a 4-Vpp full-scale input. Using a low-noise 16-bit front-end stage followed by a 14-bit ADC, the device gives 85-dBFS SNR up to 10 MHz and better than 80-dBFS SNR up to 30 MHz.

ADS5263 has a 14-bit low power mode, where it operates as a quad-channel 14-bit ADC. The 16-bit front-end stage is powered down and the part consumes almost half the power, compared to the 16-bit mode. The 14-bit mode supports a 2-Vpp full-scale input signal, with typical 74-dBFS SNR. The ADS5263 can be dynamically switched between the two resolution modes. This allows systems to use the same part in a high-resolution, high-power mode or a low-resolution, low-power mode.

The device also has a digital processing block that integrates several commonly used digital functions, such as digital gain (up to 12 dB). It includes a digital filter module that has built-in decimation filters (with low-pass, high-pass and band-pass characteristics). The decimation rate is also programmable (by 2, by 4, or by 8). This makes it very useful for narrow-band applications, where the filters can be used to improve SNR and knock-off harmonics, while at the same time reducing the output data rate.

The device includes an averaging mode where two channels (or even four channels) can be averaged to improve SNR. A very unique feature is the programmable mapper module that allows flexible mapping between the input channels and the LVDS output pins. This helps to greatly reduce the complexity of LVDS output routing and can potentially result in cheaper system boards by reducing the number of PCB layers. Specification of device is over industrial temperature range of –40°C to 85°C.

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Technical documentation

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Type Title Date
* Data sheet ADS5263 Quad Channel 16-Bit, 100-MSPS High-SNR ADC datasheet (Rev. D) PDF | HTML 30 Nov 2015
Application note High Speed ADCs and Amplifiers for Flow Cytometry Applications 12 Oct 2020
Application note Introduction to Magnetic Resonance Imaging (MRI) 14 Sep 2017
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 22 May 2015
EVM User's guide ADS5263EVM Evaluation Module (Rev. A) 05 Mar 2015
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 19 Jul 2013
Application note Understanding Serial LVDS Capture in High-Speed ADCs 10 Jul 2013
More literature TI and Altera Ease Design Process with Compatible Evaluation Tools 25 Apr 2011
More literature TI and Xilinx Ease Design Process with Compatible Evaluation Tools 25 Apr 2011
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 08 Jun 2008

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADS5263EVM — ADS5263 Evaluation Module

ADS5263 is a four channel, 16-bit ADC with up to 100 MSPS sampling frequency that delivers a SNR of 84.6 dBFS with 10 MHz input. ADS5263EVM provides a flexible environment for testing the ADS5263 under a variety of clock and input conditions. This EVM allows customers to design their own filters, (...)

User guide: PDF
Not available on TI.com
GUI for evaluation module (EVM)

ADS5263EVM GUI Installer v2.2 (Rev. A)

SLAC476A.ZIP (127271 KB)
lock = Requires export approval (1 minute)
Simulation model

ADS5263 IBIS Model

SLAM080.ZIP (26 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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VQFN (RGC) 64 View options

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