All trademarks are the property of their respective owners.
The ADS821 is a low-power, monolithic 10-bit, 40MHz Analog-to-Digital (A/D) converter utilizing a small geometry CMOS process. This complete converter includes a 10-bit quantizer with internal track-and-hold, reference, and a power down feature. It operates from a single +5V power supply and can be configured to accept either differential or single-ended input signals.
The ADS821 employs digital error correction to provide excellent Nyquist differential linearity performance for demanding imaging applications. Its low distortion, high SNR, and high oversampling capability give it the extra margin needed for telecommunications and video applications.
This high-performance converter is specified for ac and DC performance at a 40MHz sampling rate. The ADS821 is available in an SO-28 package.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | 10-Bit, 40MHz Sampling Analog-To-Digital Converter datasheet (Rev. B) | Feb 14, 2005 | |
| Application note | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | Sep 10, 2010 | ||
| Application note | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | Apr 28, 2009 | ||
| Application note | CDCE62005 as Clock Solution for High-Speed ADCs | Sep 4, 2008 | ||
| Application note | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | Jun 8, 2008 | ||
| Application note | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | Jun 2, 2008 | ||
| Analog design Journal | ADS82x ADC with non-uniform sampling clock | Feb 28, 2005 |
For additional terms or required resources, click any title below to view the detail page where available.
The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)
JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| SOIC (DW) | 28 | Ultra Librarian |
Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.
If you have questions about quality, packaging or ordering TI products, see TI support.