12-Bit, 65-MSPS, 1.0-GHz Input Bandwidth Analog-to-Digital Converter (ADC)


Product details


Sample rate (Max) (MSPS) 65 Resolution (Bits) 12 Number of input channels 1 Interface type Parallel CMOS Analog input BW (MHz) 1000 Features Low Power Rating Catalog Input range (Vp-p) 2.25 Power consumption (Typ) (mW) 400 Architecture Pipeline SNR (dB) 68.5 ENOB (Bits) 11.3 SFDR (dB) 81 Operating temperature range (C) -40 to 85 Input buffer No open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

HTQFP (PHP) 48 81 mm² 9 x 9 open-in-new Find other High-speed ADCs (>10MSPS)


  • 12-Bit Resolution
  • 65-MSPS Maximum Sample Rate
  • 2-Vpp Differential Input Range
  • 3.3-V Single Supply Operation
  • 1.8-V to 3.3-V Output Supply
  • 400-mW Total Power Dissipation
  • Two’s Complement Output Format
  • On-Chip S/H and Duty Cycle Adjust Circuit
  • Internal or External Reference
  • 48-Pin TQFP Package With PowerPad
    (7 mm x 7 mm body size)
  • 64.5-dBFS SNR and 72-dBc SFDR at 65 MSPS and 190-MHz Input
  • Power-Down Mode
  • Single-Ended or Differential Clock
  • 1-GHz -3-dB Input Bandwidth
    • High IF Sampling Receivers
    • Medical Imaging
    • Portable Instrumentation

CommsADC is a trademark of Texas Instruments.

open-in-new Find other High-speed ADCs (>10MSPS)


The ADS5413 is a low power, 12-bit, 65-MSPS, CMOS pipeline analog-to-digital converter (ADC) that operates from a single 3.3-V supply, while offering the choice of digital output levels from 1.8 V to 3.3 V. The low noise, high linearity, and low clock jitter makes the ADC well suited for high-input frequency sampling applications. On-chip duty cycle adjust circuit allows the use of a non-50% duty cycle. This can be bypassed for applications requiring low jitter or asynchronous sampling. The device can also be clocked with single ended or differential clock, without change in performance. The internal reference can be bypassed to use an external reference to suit the accuracy and low drift requirements of the application.

The device is specified over full temperature range (–40°C to +85°C).

open-in-new Find other High-speed ADCs (>10MSPS)

Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 15
Type Title Date
* Datasheet ADS5413: 12-bit, 65 MSPS CommsADC Analog-to-Digital Converter datasheet Dec. 16, 2003
Technical articles How to achieve fast frequency hopping Mar. 03, 2019
Technical articles RF sampling: Learning more about latency Feb. 09, 2017
Technical articles Why phase noise matters in RF sampling converters Nov. 28, 2016
Technical articles How to minimize filter loss when you drive an ADC Oct. 20, 2016
Application notes Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) May 22, 2015
Application notes Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) Jul. 19, 2013
Application notes High-Speed, Analog-to-Digital Converter Basics Jan. 11, 2012
Application notes Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) Sep. 10, 2010
Application notes Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio Apr. 28, 2009
Application notes CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters Jun. 08, 2008
Application notes Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 Jun. 02, 2008
Application notes Standard Procedure Direct Measurement Sub-picosecond RMS Jitter High-Speed ADC Jun. 30, 2004
Application notes How to Calculate the Period Jitter from the SSCR for High-Speed ADCs Dec. 17, 2003
User guides ADS5413 EVM User's Guide Dec. 11, 2003

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Software development

SBAC120.ZIP (262219 KB)

Design tools & simulation

PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
Analog-to-digital converter (ADC) harmonic calculator

    The ADC Harmonic Calculation tool is an excel based calculator for determining the location in frequency space of high order harmonics following Nyquist aliasing in an analog to digital converter.

    Given an ADC sample rate and the span of a signal of interest the calcultor will determine if the 2nd (...)

Jitter and SNR Calculator for ADCs
JITTER-SNR-CALC JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.
SBAC119B.ZIP (3547 KB)

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