ADS930

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8-Bit, 30 MSPS ADC SE/Diff Inputs w/ Internal Ref. and Low Power, Powerdown

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Product details

Parameters

Sample rate (Max) (MSPS) 30 Resolution (Bits) 8 Number of input channels 1 Interface type Parallel CMOS Analog input BW (MHz) 100 Features Low Power Rating Catalog Input range (Vp-p) 1, 2 Power consumption (Typ) (mW) 66 Architecture Pipeline SNR (dB) 46 ENOB (Bits) 7.1 SFDR (dB) 50 Operating temperature range (C) -40 to 85 Input buffer No open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

SSOP (DB) 28 54 mm² 5.3 x 10.2 open-in-new Find other High-speed ADCs (>10MSPS)

Features

  • +3V TO +5V SUPPLY OPERATION
  • INTERNAL REFERENCE
  • SINGLE-ENDED INPUT RANGE: 1V to 2V
  • LOW POWER: 66mW at +3V
  • HIGH SNR: 46dB
  • LOW DNL: 0.4LSB
  • SSOP-28 PACKAGE
  • APPLICATIONS
    • BATTERY POWERED EQUIPMENT
    • CAMCORDERS
    • PORTABLE TEST EQUIPMENT
    • COMPUTER SCANNERS
    • COMMUNICATIONS
open-in-new Find other High-speed ADCs (>10MSPS)

Description

The ADS930 is a high speed pipelined Analog-to-Digital Converter (ADC) specified to operate from nominal +3V or +5V power supplies with tolerances of up to 10%. This complete converter includes a high bandwidth track/hold, a 8-bit quantizer and an internal reference.

The ADS930 employs digital error correction techniques to provide excellent differential linearity for demanding imaging applications. Its low distortion and high SNR give the extra margin needed for telecommunications, video and test instrumentation applications.

This high performance ADC is specified for performance at a 30MHz sampling rate. The ADS930 is available in a SSOP-28 package.

open-in-new Find other High-speed ADCs (>10MSPS)
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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet ADS930: SpeedPlus? 8-Bit, 30MHz Sampling Analog-To-Digital Converter datasheet (Rev. A) Feb. 23, 2001
Technical articles How to achieve fast frequency hopping Mar. 03, 2019
Technical articles RF sampling: Learning more about latency Feb. 09, 2017
Technical articles Why phase noise matters in RF sampling converters Nov. 28, 2016
Technical articles How to minimize filter loss when you drive an ADC Oct. 20, 2016
Application notes Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) Sep. 10, 2010
Application notes Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio Apr. 28, 2009
Application notes CDCE62005 as Clock Solution for High-Speed ADCs Sep. 04, 2008
Application notes CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters Jun. 08, 2008
Application notes Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 Jun. 02, 2008

Design & development

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Design tools & simulation

SIMULATION TOOLS Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
CALCULATION TOOLS Download
Jitter and SNR Calculator for ADCs
JITTER-SNR-CALC JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.

CAD/CAE symbols

Package Pins Download
SSOP (DB) 28 View options

Ordering & quality

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