ADS62P19

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Dual-Channel, 11-Bit, 250-MSPS Analog-to-Digital Converter (ADC)

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Product details

Parameters

Sample rate (Max) (MSPS) 250 Resolution (Bits) 11 Number of input channels 2 Analog input BW (MHz) 700 Features High Performance Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 1250 Architecture Pipeline SNR (dB) 66.5 ENOB (Bits) 10.6 SFDR (dB) 98 Operating temperature range (C) -40 to 85 Input buffer No open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

VQFN (RGC) 64 81 mm² 9 x 9 open-in-new Find other High-speed ADCs (>10MSPS)

Features

  • Maximum Sample Rate: 250 MSPS
  • 11-Bit Resolution
  • Total Power: 1.25 W at 250 MSPS
  • Output Options:
    • DDR LVDS and Parallel CMOS
  • Programmable Gain:
    • Up to 6 dB for SNR and SFDR Trade-Off
  • DC Offset Correction
  • Crosstalk: 90 dB
  • Supports Input Clock Amplitude Down to
    400 mVPP, Differential
  • Internal and External Reference Support
  • Package: 9-mm × 9-mm QFN-64

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open-in-new Find other High-speed ADCs (>10MSPS)

Description

The ADS62P19 is part of a family of dual-channel, 11-bit, analog-to-digital converters (ADCs) with sampling rates up to 250 MSPS. The device combines high dynamic performance and low power consumption in a compact QFN-64 package. This functionality makes the device well-suited for multi-carrier, wide-bandwidth communication applications.

The ADS62P19 has gain options that can be used to improve spurious-free dynamic range (SFDR) performance at lower full-scale input ranges. The device includes a dc offset correction loop that can be used to cancel ADC offset. Both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel complementary metal oxide semiconductor (CMOS) digital output interfaces are available.

Although the device includes internal references, the traditional reference pins and associated decoupling capacitors are eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to +85°C).

open-in-new Find other High-speed ADCs (>10MSPS)
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Technical documentation

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Type Title Date
* Datasheet Dual-Channel, 11-Bit, 250-MSPS ADC With DDR LVDS and Parallel CMOS Outputs datasheet Apr. 30, 2013
Technical articles How to achieve fast frequency hopping Mar. 03, 2019
Technical articles RF sampling: Learning more about latency Feb. 09, 2017
Technical articles Why phase noise matters in RF sampling converters Nov. 28, 2016
Technical articles How to minimize filter loss when you drive an ADC Oct. 20, 2016
Application notes Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) May 22, 2015
Application notes Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) Jul. 19, 2013
More literature TI and Altera Ease Design Process with Compatible Evaluation Tools Apr. 25, 2011
More literature TI and Xilinx Ease Design Process with Compatible Evaluation Tools Apr. 25, 2011

Design & development

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Design tools & simulation

SIMULATION MODELS Download
SLWC088B.ZIP (653 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
VQFN (RGC) 64 View options

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