Product details

Sample rate (Max) (MSPS) 65 Resolution (Bits) 12 Number of input channels 2 Interface type Parallel CMOS Analog input BW (MHz) 300 Features Low Power Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 335 Architecture Pipeline SNR (dB) 70.7 ENOB (Bits) 11.3 SFDR (dB) 86 Operating temperature range (C) -40 to 85 Input buffer No
Sample rate (Max) (MSPS) 65 Resolution (Bits) 12 Number of input channels 2 Interface type Parallel CMOS Analog input BW (MHz) 300 Features Low Power Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 335 Architecture Pipeline SNR (dB) 70.7 ENOB (Bits) 11.3 SFDR (dB) 86 Operating temperature range (C) -40 to 85 Input buffer No
TQFP (PAG) 64 144 mm² 12 x 12
  • Single +3.3V Supply
  • High SNR: 70.7dBFS at fIN = 5MHz
  • Total Power Dissipation:
    Internal Reference: 371mW
    External Reference: 335mW
  • Internal or External Reference
  • Low DNL: ±0.3LSB
  • Flexible Input Range: 1.5VPP to 2VPP
  • TQFP-64 Package
  • APPLICATIONS
    • Communications IF Processing
    • Communications Base Stations
    • Test Equipment
    • Medical Imaging
    • Video Digitizing
    • CCD Digitizing

All trademarks are the property of their respective owners.

  • Single +3.3V Supply
  • High SNR: 70.7dBFS at fIN = 5MHz
  • Total Power Dissipation:
    Internal Reference: 371mW
    External Reference: 335mW
  • Internal or External Reference
  • Low DNL: ±0.3LSB
  • Flexible Input Range: 1.5VPP to 2VPP
  • TQFP-64 Package
  • APPLICATIONS
    • Communications IF Processing
    • Communications Base Stations
    • Test Equipment
    • Medical Imaging
    • Video Digitizing
    • CCD Digitizing

All trademarks are the property of their respective owners.

The ADS5232 is a dual, high-speed, high dynamic range, 12-bit pipelined analog-to-digital converter (ADC). This converter includes a high-bandwidth sample-and-hold amplifier that gives excellent spurious performance up to and beyond the Nyquist rate. The differential nature of the sample-and-hold amplifier and ADC circuitry minimizes even-order harmonics and gives excellent common-mode noise immunity.

The ADS5232 provides for setting the full-scale range of the converter without any external reference circuitry. The internal reference can be disabled, allowing low-drive, external references to be used for improved tracking in multichannel systems.

The ADS5232 provides an over-range indicator flag to indicate an input signal that exceeds the full-scale input range of the converter. This flag can be used to reduce the gain of front-end gain control circuitry. There is also an output enable pin to allow for multiplexing and testing on a PC board.

The ADS5232 employs digital error correction techniques to provide excellent differential linearity for demanding imaging applications. The ADS5232 is available in a TQFP-64 package.

The ADS5232 is a dual, high-speed, high dynamic range, 12-bit pipelined analog-to-digital converter (ADC). This converter includes a high-bandwidth sample-and-hold amplifier that gives excellent spurious performance up to and beyond the Nyquist rate. The differential nature of the sample-and-hold amplifier and ADC circuitry minimizes even-order harmonics and gives excellent common-mode noise immunity.

The ADS5232 provides for setting the full-scale range of the converter without any external reference circuitry. The internal reference can be disabled, allowing low-drive, external references to be used for improved tracking in multichannel systems.

The ADS5232 provides an over-range indicator flag to indicate an input signal that exceeds the full-scale input range of the converter. This flag can be used to reduce the gain of front-end gain control circuitry. There is also an output enable pin to allow for multiplexing and testing on a PC board.

The ADS5232 employs digital error correction techniques to provide excellent differential linearity for demanding imaging applications. The ADS5232 is available in a TQFP-64 package.

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Technical documentation

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Type Title Date
* Data sheet Dual, 12-Bit, 65MSPS, +3.3V Analog-to-Digital Converter datasheet (Rev. A) 28 Mar 2006
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 22 May 2015
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 19 Jul 2013
Application note Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) 10 Sep 2010
Application note Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio 28 Apr 2009
Application note CDCE62005 as Clock Solution for High-Speed ADCs 04 Sep 2008
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 08 Jun 2008
Application note Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 02 Jun 2008
EVM User's guide ADS5231/32/37 EVM (Rev. B) 14 Nov 2007
EVM User's guide ADS5231/32EVM User's Guide (Rev. A) 26 Jun 2007

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