ADS127L11
24-bit, 400-kSPS, delta-sigma ADC with easy-to-drive inputs and wideband or low-latency filters
ADS127L11
- Programmable data rate:
- Up to 400 kSPS (wideband filter)
- Up to 1.067 MSPS (low-latency filter)
- Selectable digital filter:
- Wideband or low-latency
- AC accuracy with dc precision:
- Dynamic range: 111.5 dB (200 kSPS)
- THD: –120 dB
- INL: 0.9 ppm of FS
- Offset drift: 50 nV/°C
- Gain drift: 0.6 ppm/°C
- Power-scalable architecture:
- High-speed mode: 400 kSPS, 18.6 mW
- Low-speed mode: 50 kSPS, 3.3 mW
- Input and reference precharge buffers
- Internal or external clock
- Functional Safety-Capable
The ADS127L11 is a 24-bit, delta-sigma (ΔΣ), analog-to-digital converter (ADC) with data rates up to 400 kSPS using the wideband filter and up to 1067 kSPS using the low-latency filter. The device offers an excellent combination of ac performance and dc precision with low power consumption (18.6 mW in high-speed mode).
The device integrates input and reference buffers to reduce signal loading. The low-drift modulator achieves excellent dc precision with low in-band noise for outstanding ac performance. The power-scalable architecture provides two speed modes to optimize data rate, resolution, and power consumption.
The digital filter is configurable for wideband or low-latency operation, allowing wideband ac performance or data throughput for dc signals to be optimized, all in one device.
The serial interface features daisy-chain capability to reduce the SPI I/O over an isolation barrier. Input and output data and register settings are validated by a cyclic-redundancy check (CRC) feature to enhance operational reliability.
The small 3-mm × 3-mm WQFN and 6.5-mm × 4.4-mm TSSOP packages are designed for limited space applications. The device is fully specified for operation over the –40°C to +125°C temperature range.
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Technical documentation
Design & development
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Package | Pins | Download |
---|---|---|
TSSOP (PW) | 20 | View options |
WQFN (RUK) | 20 | View options |
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